\subsection{Other special-purpose mapping commands}
\begin{frame}{\subsecname}
-TBD
+\begin{block}{\tt dfflibmap}
+This command maps the internal register cell types to the register types
+described in a liberty file.
+\end{block}
+
+\bigskip
+\begin{block}{\tt hilomap}
+Some architectures require special driver cells for driving a constant hi or lo
+value. This command replaces simple constants with instances of such driver cells.
+\end{block}
+
+\bigskip
+\begin{block}{\tt iopadmap}
+Top-level input/outputs must usually be implemented using special I/O-pad cells.
+This command inserts this cells to the design.
+\end{block}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+\subsection{Example Synthesis Script}
+
+\begin{frame}[fragile]{\subsecname}
+\begin{columns}
+\column[t]{4cm}
+\begin{lstlisting}[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont]
+# read and elaborate design
+read_verilog cpu_top.v cpu_ctrl.v cpu_regs.v
+read_verilog -D WITH_MULT cpu_alu.v
+hierarchy -check -top cpu_top
+
+# high-level synthesis
+proc; opt; memory -nomap;; fsm; opt
+
+# substitute block rams
+techmap -map map_rams.v
+
+# map remaining memories
+memory_map
+
+# low-level synthesis
+techmap; opt; flatten;; abc -lut6
+techmap -map map_xl_cells.v
+
+# add clock buffers
+select -set xl_clocks t:FDRE %x:+FDRE[C] t:FDRE %d
+iopadmap -inpad BUFGP O:I @xl_clocks
+
+# add io buffers
+select -set xl_nonclocks w:* t:BUFGP %x:+BUFGP[I] %d
+iopadmap -outpad OBUF I:O -inpad IBUF O:I @xl_nonclocks
+
+# write synthesis results
+write_edif synth.edif
+\end{lstlisting}
+\column[t]{6cm}
+\begin{block}{Teaser / Outlook}
+\small\parbox{6cm}{
+This script contains some constructs that have not been explained
+so far, such as the weird {\tt select} expressions at the end of
+the script. They are only one of the topics covered in Section 3
+``Advanced Synthesis'' of this presentation.}
+\end{block}
+\end{columns}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Example Problem}
+
+\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v}
+\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v}
+\end{frame}
+
+\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib}
+\begin{columns}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib}
+\end{columns}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
\subsection{Example Synthesis Script}
\begin{frame}[t]{\subsecname}
\begin{minipage}[t]{6cm}
\tt\scriptsize
\# read design\\
-\boxalert<1>{read\_verilog mydesign.v}\\
-\boxalert<2>{hierarchy -check -top mytop}
+\boxalert<1>{read\_verilog counter.v}\\
+\boxalert<2>{hierarchy -check -top counter}
\medskip
\# the high-level stuff\\
\vskip1cm
\begin{block}{Command: \tt
-\only<1>{read\_verilog mydesign.v}%
-\only<2>{hierarchy -check -top mytop}%
+\only<1>{read\_verilog counter.v}%
+\only<2>{hierarchy -check -top counter}%
\only<3>{proc}%
\only<4>{opt}%
\only<5>{memory}%
\only<13>{clean}%
\only<14>{write\_verilog synth.v}}
\only<1>{
- TBD
+ Read Verilog source file and convert to internal representation.
}%
\only<2>{
- TBD
+ Elaborate the design hierarchy. Should alsways be the first
+ command after reading the design.
}%
\only<3>{
- TBD
+ Convert ``processes'' (the internal representation of behavioral
+ Verilog code) into multiplexers and registers.
}%
\only<4>{
- TBD
+ Perform some basic optimizations and cleanups.
}%
\only<5>{
- TBD
+ Analyze memories and create circuits to implement them.
}%
\only<6>{
- TBD
+ Perform some basic optimizations and cleanups.
}%
\only<7>{
- TBD
+ Analyze and optimize finite state machines.
}%
\only<8>{
- TBD
+ Perform some basic optimizations and cleanups.
}%
\only<9>{
- TBD
+ Map coarse-grain RTL cells (adders, etc.) to fine-grain
+ logic gates (AND, OR, NOT, etc.).
}%
\only<10>{
- TBD
+ Perform some basic optimizations and cleanups.
}%
\only<11>{
- TBD
+ Map registers to available hardware flip-flops.
}%
\only<12>{
- TBD
+ Map logix to available hardware gates.
}%
\only<13>{
- TBD
+ Clean up the design (just the last step of {\tt opt}).
}%
\only<14>{
- TBD
+ Write final synthesis result to output file.
}%
\end{block}
\subsection{Running the Synthesis Script}
-\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v}
-\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v}
-\end{frame}
-
-\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib}
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib}
-\end{columns}
-\end{frame}
-
\begin{frame}[t, fragile]{\subsecname{} -- Step 1/4}
\begin{verbatim}
read_verilog counter.v
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsection{More Yosys Commands}
+\subsection{Yosys Commands}
\begin{frame}[fragile]{\subsecname{} 1/3}
Command reference:
projects / yosys.git / commitdiff