#define PCI_CHIP_RV730_948F 0x948F
#define PCI_CHIP_RV730_9490 0x9490
#define PCI_CHIP_RV730_9491 0x9491
+#define PCI_CHIP_RV730_9495 0x9495
#define PCI_CHIP_RV730_9498 0x9498
#define PCI_CHIP_RV730_949C 0x949C
#define PCI_CHIP_RV730_949E 0x949E
#define PCI_CHIP_RV710_9552 0x9552
#define PCI_CHIP_RV710_9553 0x9553
#define PCI_CHIP_RV710_9555 0x9555
+#define PCI_CHIP_RV710_9557 0x9557
#define PCI_CHIP_RV740_94A0 0x94A0
#define PCI_CHIP_RV740_94A1 0x94A1
+#define PCI_CHIP_RV740_94A3 0x94A3
#define PCI_CHIP_RV740_94B1 0x94B1
#define PCI_CHIP_RV740_94B3 0x94B3
+#define PCI_CHIP_RV740_94B4 0x94B4
#define PCI_CHIP_RV740_94B5 0x94B5
+#define PCI_CHIP_RV740_94B9 0x94B9
enum {
CHIP_FAMILY_R100,
case PCI_CHIP_RV730_948F:
case PCI_CHIP_RV730_9490:
case PCI_CHIP_RV730_9491:
+ case PCI_CHIP_RV730_9495:
case PCI_CHIP_RV730_9498:
case PCI_CHIP_RV730_949C:
case PCI_CHIP_RV730_949E:
case PCI_CHIP_RV710_9552:
case PCI_CHIP_RV710_9553:
case PCI_CHIP_RV710_9555:
+ case PCI_CHIP_RV710_9557:
screen->chip_family = CHIP_FAMILY_RV710;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;
case PCI_CHIP_RV740_94A0:
case PCI_CHIP_RV740_94A1:
+ case PCI_CHIP_RV740_94A3:
case PCI_CHIP_RV740_94B1:
case PCI_CHIP_RV740_94B3:
+ case PCI_CHIP_RV740_94B4:
case PCI_CHIP_RV740_94B5:
+ case PCI_CHIP_RV740_94B9:
screen->chip_family = CHIP_FAMILY_RV740;
screen->chip_flags = RADEON_CHIPSET_TCL;
break;