(no commit message)

diff --git a/openpower/sv/rfc/ls008.mdwn b/openpower/sv/rfc/ls008.mdwn
index 57ad4d6236ec523ab1e65e6d2b95f0f7c581e9f8..40d0b142d894a176d45c650aa6d95926402bae57 100644 (file)
--- a/openpower/sv/rfc/ls008.mdwn
+++ b/openpower/sv/rfc/ls008.mdwn
@@ -157,20 +157,6 @@ Special Registers Altered:
 
     CR0                     (if Rc=1)
 
-
-
-* `SVi=1`: test inner middle and outer
-  loop end conditions from SVSTATE0 and store in CR.EQ CR.LE CR.GT
-* `SVi=2`: test SVSTATE1 (and return conditions)
-* `SVi=3`: test SVSTATE2 (and return conditions)
-* `SVi=4`: test SVSTATE3 (and return conditions)
-* `SVi=5`: `SVSTATE.srcstep` is returned.
-* `SVi=6`: `SVSTATE.dststep` is returned.
-* `SVi=12`: `SVSTATE.pack` is set to zero and `SVSTATE.unpack` set to zero
-* `SVi=13`: `SVSTATE.pack` is set to zero and `SVSTATE.unpack` set to zero
-* `SVi=14`: `SVSTATE.pack` is set to zero and `SVSTATE.unpack` set to zero
-* `SVi=15`: `SVSTATE.pack` is set to zero and `SVSTATE.unpack` set to zero
-
 **Description**
 
 svstep may be used
@@ -178,6 +164,7 @@ to enquire about the REMAP Schedule and it may be used to alter Vectorisation
 State.  When `vf=1` then stepping occurs.
 When `vf=0` the enquiry is performed without altering internal
 state.  If `SVi=0, Rc=0, vf=0` the instruction is a `nop`.
+
 The following Modes exist:
 
 * `SVi=0`: appropriately step srcstep, dststep, subsrcstep and subdststep to the next