Fix LUT6_2 definition.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 315fd54c83d3e1866e2a050b98ff50d61db493ef..c96e0d8f16d654bd8e464bb1d696b99ee8857805 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -149,9 +149,9 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
   assign O6 = I0 ? s1[1] : s1[0];
 
   wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
-  wire [ 7: 0] s5_3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
-  wire [ 3: 0] s5_2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
-  wire [ 1: 0] s5_1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
+  wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
+  wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
+  wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
   assign O5 = I0 ? s5_1[1] : s5_1[0];
 endmodule