i965/fs: Use type-W for immediate in SampleID setup.

Not a functional difference, but register is loaded with a signed
immediate (V) and added to a signed type (D) producing a signed result
(D).

Also change the type of g0 to allow for compaction.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 1c96cf2d85be2e91272717c5bd75e9a70e3216b7..3cb8190b02a17aaba2178597b52c0a2646785d92 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1284,7 +1284,7 @@ fs_visitor::emit_sampleid_setup()
    if (key->compute_sample_id) {
       fs_reg t1 = vgrf(glsl_type::int_type);
       fs_reg t2 = vgrf(glsl_type::int_type);
-      t2.type = BRW_REGISTER_TYPE_UW;
+      t2.type = BRW_REGISTER_TYPE_W;
 
       /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
        * 8x multisampling, subspan 0 will represent sample N (where N
@@ -1306,7 +1306,7 @@ fs_visitor::emit_sampleid_setup()
        * subspan 1, and finally sample 1 of subspan 1.
        */
       abld.exec_all()
-          .AND(t1, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)),
+          .AND(t1, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
                fs_reg(0xc0));
       abld.exec_all().SHR(t1, t1, fs_reg(5));
 

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index b016b5684e78884cb7d0b2f3b12a6a9be6b728c3..20461e8bc5bcef84a6137885510e498e8fcdbe4f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1508,7 +1508,7 @@ fs_generator::generate_set_sample_id(fs_inst *inst,
    brw_set_default_exec_size(p, BRW_EXECUTE_8);
    brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
    brw_set_default_mask_control(p, BRW_MASK_DISABLE);
-   struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
+   struct brw_reg reg = stride(src1, 1, 4, 0);
    if (dispatch_width == 8) {
       brw_ADD(p, dst, src0, reg);
    } else if (dispatch_width == 16) {