enable use of svremap "persist" mode, remove 4 instructions from FFT example

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index caa0684de8188631399ab14193c397443a9ba926..47da1022d34fbd396d3e1dbc9dddae348e6ccb50 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1154,10 +1154,11 @@ class ISACaller:
         # for when SVREMAP is active, using pre-arranged schedule.
         # note: modifying PowerDecoder2 needs to "settle"
         remap_en = self.svstate.SVme
-        active = self.last_op_svshape and remap_en != 0
+        persist = self.svstate.RMpst
+        active = (persist or self.last_op_svshape) and remap_en != 0
         yield self.dec2.remap_active.eq(remap_en if active else 0)
         yield Settle()
-        if self.is_svp64_mode and self.last_op_svshape:
+        if self.is_svp64_mode and (persist or self.last_op_svshape):
             # get four SVSHAPEs. here we are hard-coding
             SVSHAPE0 = self.spr['SVSHAPE0']
             SVSHAPE1 = self.spr['SVSHAPE1']

diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py
index bbfe084586e21a3af1da8780e2db2172e6e5be1f..37c72f4919cc407a9afd994f685f4fd5e804e3db 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_fft.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py
@@ -517,25 +517,21 @@ class FFTTestCase(FHDLTestCase):
                         # tpre
                         "svremap 5, 1, 0, 2, 0, 0, 1",
                         "sv.fmuls 24, 0.v, 16.v",    # mul1_r = r*cos_r
-                        "svremap 5, 1, 0, 2, 0, 0, 1",
                         "sv.fmadds 24, 8.v, 20.v, 24", # mul2_r = i*sin_i
                                                      # tpre = mul1_r + mul2_r
                         # tpim
-                         "svremap 5, 1, 0, 2, 0, 0, 1",
                         "sv.fmuls 26, 0.v, 20.v",    # mul1_i = r*sin_i
-                         "svremap 5, 1, 0, 2, 0, 0, 1",
                         "sv.fmsubs 26, 8.v, 16.v, 26", # mul2_i = i*cos_r
                                                      # tpim = mul2_i - mul1_i
                         # vec_r jh/jl
                          "svremap 26, 0, 0, 0, 0, 1, 1",
                         "sv.ffadds 0.v, 24, 0.v",    # vh/vl +/- tpre
                         # vec_i jh/jl
-                         "svremap 26, 0, 0, 0, 0, 1, 1",
                         "sv.ffadds 8.v, 26, 8.v",    # vh/vl +- tpim
 
                         # svstep loop
                         "setvl. 0, 0, 1, 1, 0, 0",
-                        "bc 4, 2, -76"
+                        "bc 4, 2, -60"
                         ])
         lst = list(lst)