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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 5488cbdaf7cc83f0c8f9be12ff5ed1ca64809b60..4a45b1db0e8261d29e79c420299dd207e902b4b5 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -935,3 +935,14 @@ utilising internal Micro-coding and other techniques to transparently
 insert MV operations
 if necessary or desired, to give the level of efficiency or performance
 required.*
+
+# Twin (implicit) result operations
+
+Some operations in the Power ISA already target two 64-bit scalar
+registers: `lq` for example. Some mathematical algorithms are more
+efficient when there are two outputs rather than one.  64-bit multiply
+for example produces a 128 bit result
+
+* [[isa/svfixedarith]]
+* [[isa/svfparith]]
+