Added $equiv cell type

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 3a56de2f7b19825884a27ceb38f76409a573486a..60e6606f8bfc43dc0e588c4b2126f22bdeb91e46 100644 (file)
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -114,6 +114,7 @@ struct CellTypes
                setup_type("$fa", {A, B, C}, {X, Y}, true);
 
                setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
+               setup_type("$equiv", {A, B}, {Y}, true);
        }
 
        void setup_internals_mem()

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index b35cbc3d1c0a76b5ea488f3b664ec6ca53a12dda..ec61cb5297a89a22d9fa0f042fa6db3082ad665b 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -905,6 +905,14 @@ namespace {
                                return;
                        }
 
+                       if (cell->type == "$equiv") {
+                               port("\\A", 1);
+                               port("\\B", 1);
+                               port("\\Y", 1);
+                               check_expected();
+                               return;
+                       }
+
                        if (cell->type == "$_BUF_")  { check_gate("AY"); return; }
                        if (cell->type == "$_NOT_")  { check_gate("AY"); return; }
                        if (cell->type == "$_AND_")  { check_gate("ABY"); return; }

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index c12d8734e44ebc8bcca60f8dfdde99a933cf7f89..43d40c73fbd2c3e5ebef946bb5e1e15213a00494 100644 (file)
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -417,7 +417,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber
 using the {\tt abc} pass.
 
 \begin{fixme}
-Add information about {\tt \$assert} cells.
+Add information about {\tt \$assert} and {\tt \$equiv} cells.
 \end{fixme}
 
 \begin{fixme}

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index f16bd6bd28cd254c45cd5a801c099cf738c69384..d0feadd8131812f48d38f90807c757844d1ef553 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1160,12 +1160,34 @@ module \$assert (A, EN);
 
 input A, EN;
 
+`ifndef SIMLIB_NOCHECKS
 always @* begin
        if (A !== 1'b1 && EN === 1'b1) begin
                $display("Assertation failed!");
-               $finish;
+               $stop;
+       end
+end
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$equiv (A, B, Y);
+
+input A, B;
+output Y;
+
+assign Y = (A !== 1'bx && A !== B) ? 1'bx : A;
+
+`ifndef SIMLIB_NOCHECKS
+always @* begin
+       if (A !== 1'bx && A !== B) begin
+               $display("Equivalence failed!");
+               $stop;
        end
 end
+`endif
 
 endmodule