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diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 5e6ffebc392a93e87d2a33abf339f278d4b5c296..2329167f474b54d608a4698dd42882e8106fbf89 100644 (file)
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -90,20 +90,17 @@ OPF ISA WG):
 |---|---- |--|-----|-----|-----|-----  |-----  |--|----      |
 |19 |RT   |  |mask |BFA  |     |XO[0:4]|XO[5:9]|/ |          |
 |19 |     |  |     |     |     |1 //// |00011  |  |rsvd      |
-|19 |RT   |M |mask |BFA  | 0 0 |1 mode |00011  |Rc|crrweird  |
-|19 |RT   |M |mask |BFA  | 0 1 |1 mode |00011  |Rc|mfcrweird |
-|19 |RA   |M |mask |BF   | 0 0 |0 mode |00011  |1 |mtcrrweird |
-|19 |RA   |M |mask |BF   | 0 1 |0 mode |00011  |0 |mtcrweird |
-|19 |BT   |M |mask |BFA  | 0 1 |0 mode |00011  |1 |crweirder |
-|19 |BF //|M |mask |BFA  | 1 1 |0 mode |00011  |0 |crweird   |
+|19 |RT   |M |mask |BFA  | 0 0 |0 mode |00011  |Rc|crrweird  |
+|19 |RT   |M |mask |BFA  | 0 1 |0 mode |00011  |Rc|mfcrweird |
+|19 |RA   |M |mask |BF   | 1 0 |0 mode |00011  |0 |mtcrrweird |
+|19 |RA   |M |mask |BF   | 1 0 |0 mode |00011  |1 |mtcrweird |
+|19 |BT   |M |mask |BFA  | 1 1 |0 mode |00011  |0 |crweirder |
 |19 |BF //|M |mask |BFA  | 1 1 |0 mode |00011  |1 |mcrfm     |
 
 **crrweird**
 
 mode is encoded in XO and is 4 bits
 
-bit 19=0, bit 20=0
-
     crrweird: RT, BFA, M, mask.mode
 
     creg = CR{BFA}
@@ -128,8 +125,6 @@ sequentially into the destination. *Destination elwidth overrides still apply*.
 
 mode is encoded in XO and is 4 bits
 
-bit 19=0, bit 20=0
-
     mfcrrweird: RT, BFA, mask.mode
 
     creg = CR{BFA}
@@ -154,8 +149,6 @@ into the destination.  *Destination elwidth overrides still apply*
 
 mode is encoded in XO and is 4 bits
 
-bit 19=0, bit 20=0
-
     mtcrrweird: BF, RA, M, mask.mode
 
     n0 = mask[0] & (mode[0] == RA[63])
@@ -173,8 +166,6 @@ Mode capability
 
 **mtcrweird**
 
-bit 19=0, bit 20=1
-
     mtcrweird: BF, RA, M, mask.mode
 
     reg = (RA|0)
@@ -198,36 +189,8 @@ When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64
 type operation that has 3-bit Data-dependent and 3-bit Predicate-result
 capability (BF is 3 bits)
 
-**crweird**
-
-bit 19=1, bit 20=0, bit 30=0
-
-    crweird: BF, BFA, M, mask.mode
-
-    creg = CR{BFA}
-    n0 = mask[0] & (mode[0] == creg[0])
-    n1 = mask[1] & (mode[1] == creg[1])
-    n2 = mask[2] & (mode[2] == creg[2])
-    n3 = mask[3] & (mode[3] == creg[3])
-    result = n0 || n1 || n2 || n3
-    if M:
-        result |= CR{BF} & ~mask
-    CR{BF} = result
-
-Note that when M=1 this operation is a Read-Modify-Write on the CR Field
-BF. Masked-out bits of the 4-bit CR Field BF will not be changed when
-M=1. Correspondingly when M=0 this operation is an overwrite: no read
-of BF is required because the masked-out bits of the BF CR Field are
-set to zero.
-
-When used with SVP64 Prefixing this is a [[openpower/sv/cr_ops]] SVP64
-type operation that has 3-bit Data-dependent and 3-bit Predicate-result
-capability (BF is 3 bits)
-
 **mcrfm** - Move CR Field, masked.
 
-bit 19=1, bit 20=0, bit 30=1
-
     mcrfm: BF, BFA, M, mask.mode
 
     result = mask & CR{BFA}
@@ -254,8 +217,6 @@ individual bits in BF may be set to 1 by ensuring that the required bit of
 
 **crweirder**
 
-bit 19=1, bit 20=1
-
     crweirder: BT, BFA, mask.mode
 
     creg = CR{BFA}