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diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index e2b202ea197d95ffbb4213900b45cea6d15dc96a..fddef935296665ebc2c55c254624d0d7653e3557 100644 (file)
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -72,7 +72,7 @@ SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
 | / | / | 00    |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
 | / | / | 00    |   1 | 1  CRM  | parallel reduce mode (mapreduce), SUBVL=1 |
 | / | / | 00    |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
-|dz |SNZ| 01/10 | inv |  CR-bit | Ffirst 3-bit mode      |
+|sz |SNZ| 01/10 | inv |  CR-bit | Ffirst 3-bit mode      |
 |sz |SNZ| 01/10 | inv |  dz /   | Ffirst 5-bit mode       |
 |sz |SNZ| 11    | inv | CR-bit  |  3-bit pred-result CR sel |
 |sz |SNZ| 11    | inv | dz  /   |  5-bit pred-result z/nonz |