}
static void
-emit_setup(struct fd_ringbuffer *ring)
+emit_setup(struct fd_batch *batch)
{
- OUT_PKT7(ring, CP_EVENT_WRITE, 1);
- OUT_RING(ring, PC_CCU_INVALIDATE_COLOR);
+ struct fd_ringbuffer *ring = batch->draw;
- OUT_PKT7(ring, CP_EVENT_WRITE, 1);
- OUT_RING(ring, LRZ_FLUSH);
-
- OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
- OUT_RING(ring, 0x0);
-
- OUT_WFI5(ring);
-
- OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
- OUT_RING(ring, 0x10000000);
+ fd6_event_write(batch, ring, 0x1d, true);
+ fd6_event_write(batch, ring, FACENESS_FLUSH, true);
+ fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
+ fd6_event_write(batch, ring, PC_CCU_INVALIDATE_DEPTH, false);
}
static uint32_t
mtx_unlock(&ctx->screen->lock);
- emit_setup(batch->draw);
+ emit_setup(batch);
if ((info->src.resource->target == PIPE_BUFFER) &&
(info->dst.resource->target == PIPE_BUFFER)) {
fd6_event_write(batch, batch->draw, 0x1d, true);
fd6_event_write(batch, batch->draw, FACENESS_FLUSH, true);
fd6_event_write(batch, batch->draw, CACHE_FLUSH_TS, true);
+ fd6_cache_inv(batch, batch->draw);
fd_resource(info->dst.resource)->valid = true;
batch->needs_flush = true;