Decoder: Remove the thread context get/set from the decoder.

This interface is no longer used, and getting rid of it simplifies the
decoders and code that sets up the decoders. The thread context had been used
to read architectural state which was used to contextualize the instruction
memory as it came in. That was changed so that the state is now sent to the
decoders to keep locally if/when it changes. That's significantly more
efficient.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

diff --git a/src/arch/alpha/decoder.hh b/src/arch/alpha/decoder.hh
index ef2f5856cd59e72cea9d7248a003b105d9504365..45e737e529a9225ad390d1dbb1561b4cbefd5b87 100644 (file)
--- a/src/arch/alpha/decoder.hh
+++ b/src/arch/alpha/decoder.hh
@@ -36,36 +36,20 @@
 #include "cpu/static_inst.hh"
 #include "sim/full_system.hh"
 
-class ThreadContext;
-
 namespace AlphaISA
 {
 
 class Decoder
 {
   protected:
-    ThreadContext *tc;
-
     // The extended machine instruction being generated
     ExtMachInst ext_inst;
     bool instDone;
 
   public:
-    Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
+    Decoder() : instDone(false)
     {}
 
-    ThreadContext *
-    getTC()
-    {
-        return tc;
-    }
-
-    void
-    setTC(ThreadContext * _tc)
-    {
-        tc = _tc;
-    }
-
     void
     process()
     { }

diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index b5a73d68b9dff1e7a286dd4a8bd17a6cad92a523..e957ce0e74ce4614053b50c7cae1d3b048b8947f 100644 (file)
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -32,7 +32,6 @@
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/utility.hh"
 #include "base/trace.hh"
-#include "cpu/thread_context.hh"
 #include "debug/Decoder.hh"
 
 namespace ArmISA

diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index 9099e3e2e2baa49db510e74b8e066513c4d3815c..83a16da4c3fcae9f5deebce3db71647c2a5e8e42 100644 (file)
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -39,15 +39,12 @@
 #include "base/types.hh"
 #include "cpu/static_inst.hh"
 
-class ThreadContext;
-
 namespace ArmISA
 {
 
 class Decoder
 {
   protected:
-    ThreadContext * tc;
     //The extended machine instruction being generated
     ExtMachInst emi;
     MachInst data;
@@ -72,23 +69,11 @@ class Decoder
         foundIt = false;
     }
 
-    Decoder(ThreadContext * _tc) : tc(_tc), data(0),
-        fpscrLen(0), fpscrStride(0)
+    Decoder() : data(0), fpscrLen(0), fpscrStride(0)
     {
         reset();
     }
 
-    ThreadContext * getTC()
-    {
-        return tc;
-    }
-
-    void
-    setTC(ThreadContext * _tc)
-    {
-        tc = _tc;
-    }
-
     void process();
 
     //Use this to give data to the decoder. This should be used

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 0df50a85e526472337c874259f88ba9b5151bc78..ee2799147636d54bff932a7d2d01ba7acba87552 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -381,7 +381,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 fpscrMask.n = ones;
                 newVal = (newVal & (uint32_t)fpscrMask) |
                          (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
-                tc->getDecodePtr()->setContext(newVal);
+                tc->getDecoderPtr()->setContext(newVal);
             }
             break;
           case MISCREG_CPSR_Q:

diff --git a/src/arch/mips/decoder.hh b/src/arch/mips/decoder.hh
index 4857eb35362e6ebbc3c142538909c9a4d20aebac..080614dee995902bd9af2ff2543feebfe70e03d9 100644 (file)
--- a/src/arch/mips/decoder.hh
+++ b/src/arch/mips/decoder.hh
@@ -37,34 +37,20 @@
 #include "base/types.hh"
 #include "cpu/static_inst.hh"
 
-class ThreadContext;
-
 namespace MipsISA
 {
 
 class Decoder
 {
   protected:
-    ThreadContext * tc;
     //The extended machine instruction being generated
     ExtMachInst emi;
     bool instDone;
 
   public:
-    Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
+    Decoder() : instDone(false)
     {}
 
-    ThreadContext *getTC()
-    {
-        return tc;
-    }
-
-    void
-    setTC(ThreadContext *_tc)
-    {
-        tc = _tc;
-    }
-
     void
     process()
     {

diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh
index 60fc8ca75c5d85a681fbc8858ada9cdfeddf2a30..830636aed103bd1ee1733d8e576f9fd8a09439a4 100644 (file)
--- a/src/arch/power/decoder.hh
+++ b/src/arch/power/decoder.hh
@@ -35,35 +35,19 @@
 #include "arch/types.hh"
 #include "cpu/static_inst.hh"
 
-class ThreadContext;
-
 namespace PowerISA
 {
 
 class Decoder
 {
   protected:
-    ThreadContext * tc;
-
     // The extended machine instruction being generated
     ExtMachInst emi;
     bool instDone;
 
   public:
-    Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
-    {
-    }
-
-    ThreadContext *
-    getTC()
-    {
-        return tc;
-    }
-
-    void
-    setTC(ThreadContext * _tc)
+    Decoder() : instDone(false)
     {
-        tc = _tc;
     }
 
     void

diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh
index f85d5e4de77803df7af6014e6ad9363337a27b46..e7a806d81bd920df54645dcbf0cce7a6c4a6f1de 100644 (file)
--- a/src/arch/sparc/decoder.hh
+++ b/src/arch/sparc/decoder.hh
@@ -35,9 +35,6 @@
 #include "arch/sparc/registers.hh"
 #include "arch/types.hh"
 #include "cpu/static_inst.hh"
-#include "cpu/thread_context.hh"
-
-class ThreadContext;
 
 namespace SparcISA
 {
@@ -45,28 +42,15 @@ namespace SparcISA
 class Decoder
 {
   protected:
-    ThreadContext * tc;
     // The extended machine instruction being generated
     ExtMachInst emi;
     bool instDone;
     MiscReg asi;
 
   public:
-    Decoder(ThreadContext * _tc) : tc(_tc), instDone(false), asi(0)
+    Decoder() : instDone(false), asi(0)
     {}
 
-    ThreadContext *
-    getTC()
-    {
-        return tc;
-    }
-
-    void
-    setTC(ThreadContext * _tc)
-    {
-        tc = _tc;
-    }
-
     void process() {}
 
     void

diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 4cfb93b0d5e158480ded5639d5452e235c1ddbf1..b8b4e88cc8cb2215dce670c37425bc6822a8bbef 100644 (file)
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -29,6 +29,7 @@
  */
 
 #include "arch/sparc/asi.hh"
+#include "arch/sparc/decoder.hh"
 #include "arch/sparc/isa.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"
@@ -550,7 +551,7 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
 
     switch (miscReg) {
       case MISCREG_ASI:
-        tc->getDecodePtr()->setContext(val);
+        tc->getDecoderPtr()->setContext(val);
         break;
       case MISCREG_STICK:
       case MISCREG_TICK:

diff --git a/src/arch/x86/decoder.cc b/src/arch/x86/decoder.cc
index 9dcb0290221f64b6cddab392eab0048862c01128..f42fb28bf48ec581ed410ee7daaabb035d759f79 100644 (file)
--- a/src/arch/x86/decoder.cc
+++ b/src/arch/x86/decoder.cc
@@ -33,7 +33,6 @@
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
-#include "cpu/thread_context.hh"
 #include "debug/Decoder.hh"
 
 namespace X86ISA

diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh
index 796f9eef98234f234eb0e60a52576c6e4f034d6e..6f55ab26f8c97ddf39fc3abfa287680b76df584e 100644 (file)
--- a/src/arch/x86/decoder.hh
+++ b/src/arch/x86/decoder.hh
@@ -44,8 +44,6 @@
 #include "cpu/static_inst.hh"
 #include "debug/Decoder.hh"
 
-class ThreadContext;
-
 namespace X86ISA
 {
 
@@ -72,7 +70,6 @@ class Decoder
 
     static InstBytes dummy;
 
-    ThreadContext * tc;
     //The bytes to be predecoded
     MachInst fetchChunk;
     InstBytes *instBytes;
@@ -205,8 +202,7 @@ class Decoder
     static InstCacheMap instCacheMap;
 
   public:
-    Decoder(ThreadContext * _tc) :
-        tc(_tc), basePC(0), origPC(0), offset(0),
+    Decoder() : basePC(0), origPC(0), offset(0),
         outOfBytes(true), instDone(false),
         state(ResetState)
     {
@@ -259,16 +255,6 @@ class Decoder
         state = ResetState;
     }
 
-    ThreadContext * getTC()
-    {
-        return tc;
-    }
-
-    void setTC(ThreadContext * _tc)
-    {
-        tc = _tc;
-    }
-
     void process();
 
     //Use this to give data to the decoder. This should be used

diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 40f1cef6ad4aad98b36e453329de4ad1706d9cf3..5637eb08b48211d611c4c93e60e7a32840ef44a8 100644 (file)
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -306,7 +306,6 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
                     StaticInstPtr instPtr = NULL;
 
                     //Predecode, ie bundle up an ExtMachInst
-                    thread->decoder.setTC(thread->getTC());
                     //If more fetch data is needed, pass it in.
                     Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
                     thread->decoder.moreBytes(pcState, fetchPC, machInst);

diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc
index 0ed59fe2d905e48dca07e0cc712edf54ed810893..49bd0434b9e9ecc619fac21c28d4eccb30c2d82d 100644 (file)
--- a/src/cpu/inorder/resources/fetch_unit.cc
+++ b/src/cpu/inorder/resources/fetch_unit.cc
@@ -59,7 +59,7 @@ FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
       instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize)
 {
     for (int tid = 0; tid < MaxThreads; tid++)
-        decoder[tid] = new Decoder(NULL);
+        decoder[tid] = new Decoder;
 }
 
 FetchUnit::~FetchUnit()
@@ -109,7 +109,6 @@ FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
     MachInst mach_inst =
         TheISA::gtoh(fetchInsts[fetch_offset]);
 
-    decoder[tid]->setTC(cpu->thread[tid]->getTC());
     decoder[tid]->moreBytes(instPC, inst->instAddr(), mach_inst);
     assert(decoder[tid]->instReady());
     inst->setStaticInst(decoder[tid]->decode(instPC));

diff --git a/src/cpu/legiontrace.cc b/src/cpu/legiontrace.cc
index f3ac5e7028cb17a3e2ad91812ca58f499280016e..b94b8f5fef7abfded6415696162cbb1df7b632f8 100644 (file)
--- a/src/cpu/legiontrace.cc
+++ b/src/cpu/legiontrace.cc
@@ -422,7 +422,6 @@ Trace::LegionTraceRecord::dump()
                          << endl;
 
                     TheISA::Decoder *decoder = thread->getDecoderPtr();
-                    decoder->setTC(thread);
                     decoder->moreBytes(m5Pc, m5Pc, shared_data->instruction);
 
                     assert(decoder->instReady());

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 33563f5396f6f79bad1551d755cc1d12ed6f81b0..9efe30309dd66ed985a2bcc9c1d53bc1ba6584d0 100644 (file)
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -134,7 +134,7 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
 
     for (int i = 0; i < Impl::MaxThreads; i++) {
         cacheData[i] = NULL;
-        decoder[i] = new TheISA::Decoder(NULL);
+        decoder[i] = new TheISA::Decoder;
     }
 }
 
@@ -1225,9 +1225,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
                 if (blkOffset >= numInsts)
                     break;
             }
-            MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
 
-            decoder[tid]->setTC(cpu->thread[tid]->getTC());
+            MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
             decoder[tid]->moreBytes(thisPC, fetchAddr, inst);
 
             if (decoder[tid]->needMoreBytes()) {

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 5a9499333fef4477bc633c97b12878e60a3abc10..9ca94390057b03101a3f094e96078c44962f3474 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -380,8 +380,6 @@ BaseSimpleCPU::preExecute()
         TheISA::Decoder *decoder = &(thread->decoder);
 
         //Predecode, ie bundle up an ExtMachInst
-        //This should go away once the constructor can be set up properly
-        decoder->setTC(thread->getTC());
         //If more fetch data is needed, pass it in.
         Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
         //if(decoder->needMoreBytes())

diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index f887e7e483a25ef3aeccf1cab0facb8fda4217f5..cf9bb4840da310b37990f2c8b4636bb9d4754460 100644 (file)
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -63,16 +63,16 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            Process *_process, TheISA::TLB *_itb,
                            TheISA::TLB *_dtb)
     : ThreadState(_cpu, _thread_num, _process), system(_sys), itb(_itb),
-      dtb(_dtb), decoder(NULL)
+      dtb(_dtb)
 {
     clearArchRegs();
     tc = new ProxyThreadContext<SimpleThread>(this);
 }
+
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            TheISA::TLB *_itb, TheISA::TLB *_dtb,
                            bool use_kernel_stats)
-    : ThreadState(_cpu, _thread_num, NULL), system(_sys), itb(_itb), dtb(_dtb),
-      decoder(NULL)
+    : ThreadState(_cpu, _thread_num, NULL), system(_sys), itb(_itb), dtb(_dtb)
 {
     tc = new ProxyThreadContext<SimpleThread>(this);
 
@@ -99,7 +99,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
 }
 
 SimpleThread::SimpleThread()
-    : ThreadState(NULL, -1, NULL), decoder(NULL)
+    : ThreadState(NULL, -1, NULL)
 {
     tc = new ProxyThreadContext<SimpleThread>(this);
 }