RADEON_LLVM_AMDGPU_HS = 93,
};
-#define CONST_ADDR_SPACE 2
-#define LOCAL_ADDR_SPACE 3
-
#define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
#define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
{
return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
- CONST_ADDR_SPACE);
+ AC_CONST_ADDR_SPACE);
}
static int get_elem_bits(struct ac_llvm_context *ctx, LLVMTypeRef type)
&user_sgpr_idx, 2);
if (ctx->options->supports_spill) {
ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
- LLVMPointerType(ctx->ac.i8, CONST_ADDR_SPACE),
+ LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
NULL, 0, AC_FUNC_ATTR_READNONE);
ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
const_array(ctx->ac.v4i32, 16), "");
LLVMAddGlobalInAddressSpace(
ctx->ac.module, glsl_to_llvm_type(ctx->nctx, variable->type),
variable->name ? variable->name : "",
- LOCAL_ADDR_SPACE);
+ AC_LOCAL_ADDR_SPACE);
_mesa_hash_table_insert(ctx->vars, variable, shared);
}
}
*/
#define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
-enum {
- CONST_ADDR_SPACE = 2,
- LOCAL_ADDR_SPACE = 3,
-};
-
static bool llvm_type_is_64bit(struct si_shader_context *ctx,
LLVMTypeRef type)
{
{
struct si_shader_selector *sel = ctx->shader->selector;
- LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
+ LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_LOCAL_ADDR_SPACE);
LLVMValueRef var;
assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
LLVMArrayType(ctx->i8, sel->local_size),
"compute_lds",
- LOCAL_ADDR_SPACE);
+ AC_LOCAL_ADDR_SPACE);
LLVMSetAlignment(var, 4);
ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
LLVMTypeRef si_const_array(LLVMTypeRef elem_type, int num_elements)
{
return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
- CONST_ADDR_SPACE);
+ AC_CONST_ADDR_SPACE);
}
static void si_llvm_emit_ddxy(