| Field Name | Field bits | Description |
|------------|------------|----------------------------------------|
| ELWIDTH | `4:5` | Element Width |
-| PACK | `4` | Pack subvectors |
-| UNPACK | `5` | Unpack subvectoes |
+| PACK | `4` | Pack subvectors (sv.setvl only) |
+| UNPACK | `5` | Unpack subvectors (sv.setvl only |
| ELWIDTH_SRC | `6:7` | Element Width for Source |
| EXTRA | `10:18` | Register Extra encoding |
| MODE | `19:23` | changes Vector behaviour |
* MODE changes the behaviour of the SV operation (result saturation, mapreduce)
* SUBVL groups elements together into vec2, vec3, vec4 for use in 3D and Audio/Video DSP work
* ELWIDTH and ELWIDTH_SRC overrides the instruction's destination and source operand width
-* PACK and UNPACK apply to Subvector structure packing
+* PACK and UNPACK apply to Subvector structure packing: may only be
+ set by the `sv.setvl` instruction.
* MASK (and MASK_SRC) and MASKMODE provide predication (two types of sources: scalar INT and Vector CR).
* Bits 10 to 18 (EXTRA) are further decoded depending on the RM category for the instruction, which is determined only by decoding the Scalar 32 bit suffix.
are therefore used for other purposes, or when Rc=1, the Elwidth
applies to the result being tested, but not to the Vector of CR Fields.
-
# SUBVL Encoding
the default for SUBVL is 1 and its encoding is 0b00 to indicate that