Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards

Just like Verilog...

diff --git a/passes/pmgen/ice40_wrapcarry.cc b/passes/pmgen/ice40_wrapcarry.cc
index d458dce46dbde02e7afcbb4a9f1ac2413bb85227..0053c8872292c4ea3dec9cd39d33c27c212eac6f 100644 (file)
--- a/passes/pmgen/ice40_wrapcarry.cc
+++ b/passes/pmgen/ice40_wrapcarry.cc
@@ -127,7 +127,7 @@ struct Ice40WrapCarryPass : public Pass {
                                        lut->setParam(ID(WIDTH), 4);
                                        lut->setParam(ID(LUT), cell->getParam(ID(LUT)));
                                        auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3));
-                                       lut->setPort(ID(A), {cell->getPort(ID(I0)), cell->getPort(ID(A)), cell->getPort(ID(B)), I3 });
+                                       lut->setPort(ID(A), { I3, cell->getPort(ID(B)), cell->getPort(ID(A)), cell->getPort(ID(I0)) });
                                        lut->setPort(ID(Y), cell->getPort(ID(O)));
 
                                        Const src;

diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 940a110636e817c57ed0a09aa1d8e09bb27ea446..925ab31bb31a6d47a8a9ec33c7c70484fe0ef4e5 100644 (file)
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -140,7 +140,7 @@ static void run_ice40_opts(Module *module)
                                                log_id(module), log_id(cell), log_signal(replacement_output));
                                cell->type = "$lut";
                                auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)));
-                               cell->setPort("\\A", { get_bit_or_zero(cell->getPort("\\I0")), inbit[0], inbit[1], I3 });
+                               cell->setPort("\\A", { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) });
                                cell->setPort("\\Y", cell->getPort("\\O"));
                                cell->unsetPort("\\B");
                                cell->unsetPort("\\CI");