mac: add interpacket gap inserter/checker

diff --git a/liteeth/common.py b/liteeth/common.py
index ec90bf0a97dd97af2299dbe38b07af602d8a546f..b94ce217559a7870891ce97f8350991c67b7e344 100644 (file)
--- a/liteeth/common.py
+++ b/liteeth/common.py
@@ -15,6 +15,7 @@ from migen.bank.description import *
 
 eth_mtu = 1532
 eth_min_len = 46
+eth_interpacket_gap = 12
 eth_preamble = 0xD555555555555555
 buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)
 

diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py
index 10a090f3a6714e504da0ece829c2b4f3b9e92caf..2b9cfb638de89d3a257d7c185af5ec3eb0691ee3 100644 (file)
--- a/liteeth/mac/__init__.py
+++ b/liteeth/mac/__init__.py
@@ -22,7 +22,7 @@ class LiteEthMACPacketizer(LiteEthPacketizer):
                        mac_header_len)
 
 class LiteEthMAC(Module, AutoCSR):
-       def __init__(self, phy, dw, interface="crossbar", endianness="be",
+       def __init__(self, phy, dw, interface="crossbar", endianness="big",
                        with_hw_preamble_crc=True):
                self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_hw_preamble_crc)
                self.csrs = []

diff --git a/liteeth/mac/core/__init__.py b/liteeth/mac/core/__init__.py
index f887c61199918a82d79424d2d57c2593e9a6b809..5db1feac7e061575ccb53ad7e021e657fc2593dd 100644 (file)
--- a/liteeth/mac/core/__init__.py
+++ b/liteeth/mac/core/__init__.py
@@ -1,5 +1,5 @@
 from liteeth.common import *
-from liteeth.mac.core import preamble, crc, last_be
+from liteeth.mac.core import gap, preamble, crc, last_be
 
 class LiteEthMACCore(Module, AutoCSR):
        def __init__(self, phy, dw, endianness="big", with_hw_preamble_crc=True):
@@ -9,6 +9,14 @@ class LiteEthMACCore(Module, AutoCSR):
                rx_pipeline = [phy]
                tx_pipeline = [phy]
 
+               # Interpacket gap
+               tx_gap_inserter = gap.LiteEthMACGap(phy.dw)
+               rx_gap_checker = gap.LiteEthMACGap(phy.dw, ack_on_gap=True)
+               self.submodules += tx_gap_inserter, rx_gap_checker
+
+               tx_pipeline += [tx_gap_inserter]
+               rx_pipeline += [rx_gap_checker]
+
                # Preamble / CRC
                if with_hw_preamble_crc:
                        self._hw_preamble_crc = CSRStatus(reset=1)

diff --git a/liteeth/mac/core/gap.py b/liteeth/mac/core/gap.py
new file mode 100644 (file)
index 0000000..0f1ddd7
--- /dev/null
+++ b/liteeth/mac/core/gap.py
@@ -0,0 +1,25 @@
+from liteeth.common import *
+
+class LiteEthMACGap(Module):
+       def __init__(self, dw, ack_on_gap=False):
+               self.sink = sink = Sink(eth_phy_description(dw))
+               self.source = source = Source(eth_phy_description(dw))
+               ###
+               gap = math.ceil(eth_interpacket_gap/(dw//8))
+               self.submodules.counter = counter = Counter(max=gap)
+
+               self.submodules.fsm = fsm = FSM(reset_state="COPY")
+               fsm.act("COPY",
+                       counter.reset.eq(1),
+                       Record.connect(sink, source),
+                       If(sink.stb & sink.eop & sink.ack,
+                               NextState("GAP")
+                       )
+               )
+               fsm.act("GAP",
+                       counter.ce.eq(1),
+                       sink.ack.eq(int(ack_on_gap)),
+                       If(counter.value == (gap-1),
+                               NextState("COPY")
+                       )
+               )