[libre-riscv-dev] [Bug 270] New: investigate nmigen clock gating
authorbugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Sat, 28 Mar 2020 14:14:45 +0000 (14:14 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Sat, 28 Mar 2020 14:14:48 +0000 (14:14 +0000)
e2/c7f0e71bf08c1603922c39285816b58164a563 [new file with mode: 0644]

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+Date: Sat, 28 Mar 2020 14:14:45 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: new
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
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+Message-ID: <bug-270-13@http.bugs.libre-riscv.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 270] New: investigate nmigen clock gating
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