mode_number // number of modes
};
-// Constants Related to the number of registers
-
-enum {
- LogVMPageSize = 13, // 8K bytes
- VMPageSize = (1 << LogVMPageSize),
-
- BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
-
- MachineBytes = 8,
- WordBytes = 4,
- HalfwordBytes = 2,
- ByteBytes = 1
-};
+const int MachineBytes = 8;
// return a no-op instruction... used for instruction fetch faults
// Alpha UNOP (ldq_u r31,0(r0))
: LiveProcess(params, objFile)
{
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
- brk_point = roundUp(brk_point, VMPageSize);
+ brk_point = roundUp(brk_point, PageBytes);
// Set up stack. On Alpha, stack goes below text section. This
// code should get moved to some architecture-specific spot.
// seem to be a problem.
// check out _dl_aux_init() in glibc/elf/dl-support.c for details
// --Lisa
- auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::VMPageSize));
+ auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::PageBytes));
auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable());
LiveProcess::initState();
- argsInit(MachineBytes, VMPageSize);
+ argsInit(MachineBytes, PageBytes);
ThreadContext *tc = system->getThreadContext(contextIds[0]);
tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
namespace LittleEndianGuest {}
-#define TARGET_ARM
-
namespace ArmISA
{
using namespace LittleEndianGuest;
// return a no-op instruction... used for instruction fetch faults
const ExtMachInst NoopMachInst = 0x01E320F000ULL;
- const int LogVMPageSize = 12; // 4K bytes
- const int VMPageSize = (1 << LogVMPageSize);
-
- // Shouldn't this be 1 because of Thumb?! Dynamic? --Ali
- const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
-
const int MachineBytes = 4;
- const int WordBytes = 4;
- const int HalfwordBytes = 2;
- const int ByteBytes = 1;
const uint32_t HighVecs = 0xFFFF0000;
// Set up break point (Top of Heap)
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
- brk_point = roundUp(brk_point, VMPageSize);
+ brk_point = roundUp(brk_point, PageBytes);
// Set up region for mmaps. For now, start at bottom of kuseg space.
mmap_start = mmap_end = 0x40000000L;
// Set up break point (Top of Heap)
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
- brk_point = roundUp(brk_point, VMPageSize);
+ brk_point = roundUp(brk_point, PageBytes);
// Set up region for mmaps. For now, start at bottom of kuseg space.
mmap_start = mmap_end = 0x4000000000L;
ArmLiveProcess32::initState()
{
LiveProcess::initState();
- argsInit<uint32_t>(VMPageSize, INTREG_SP);
+ argsInit<uint32_t>(PageBytes, INTREG_SP);
for (int i = 0; i < contextIds.size(); i++) {
ThreadContext * tc = system->getThreadContext(contextIds[i]);
CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
ArmLiveProcess64::initState()
{
LiveProcess::initState();
- argsInit<uint64_t>(VMPageSize, INTREG_SP0);
+ argsInit<uint64_t>(PageBytes, INTREG_SP0);
for (int i = 0; i < contextIds.size(); i++) {
ThreadContext * tc = system->getThreadContext(contextIds[i]);
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
//XXX Figure out what these should be
auxv.push_back(auxv_t(M5_AT_HWCAP, features));
//The system page size
- auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::VMPageSize));
+ auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::PageBytes));
//Frequency at which times() increments
auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64));
// For statically linked executables, this is the virtual address of the
}
} else {
if (size == (uint16_t)(-1))
+ // todo: should this not be sizeof(uint32_t) rather?
size = ArmISA::MachineBytes;
if (number < NumArgumentRegs) {
// return a no-op instruction... used for instruction fetch faults
const ExtMachInst NoopMachInst = 0x00000000;
-const int LogVMPageSize = 13; // 8K bytes
-const int VMPageSize = (1 << LogVMPageSize);
-
-const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
-
-const int MachineBytes = 4;
-const int WordBytes = 4;
-const int HalfwordBytes = 2;
-const int ByteBytes = 1;
-
const int ANNOTE_NONE = 0;
const uint32_t ITOUCH_ANNOTE = 0xffffffff;
// Set up break point (Top of Heap)
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
- brk_point = roundUp(brk_point, VMPageSize);
+ brk_point = roundUp(brk_point, PageBytes);
// Set up region for mmaps. Start it 1GB above the top of the heap.
mmap_start = mmap_end = brk_point + 0x40000000L;
{
LiveProcess::initState();
- argsInit<uint32_t>(VMPageSize);
+ argsInit<uint32_t>(PageBytes);
}
template<class IntType>
if (elfObject)
{
// Set the system page size
- auxv.push_back(auxv_t(M5_AT_PAGESZ, MipsISA::VMPageSize));
+ auxv.push_back(auxv_t(M5_AT_PAGESZ, MipsISA::PageBytes));
// Set the frequency at which time() increments
auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
// For statically linked executables, this is the virtual
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
- const int LogVMPageSize = 12; // 4K bytes
- const int VMPageSize = (1 << LogVMPageSize);
-
}
#endif //__ARCH_NULL_ISA_TRAITS_HH__
const Addr NPtePage = ULL(1) << NPtePageShift;
const Addr PteMask = NPtePage - 1;
-const int LogVMPageSize = 12; // 4K bytes
-const int VMPageSize = (1 << LogVMPageSize);
-
const int MachineBytes = 4;
// This is ori 0, 0, 0
// Set up break point (Top of Heap)
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
- brk_point = roundUp(brk_point, VMPageSize);
+ brk_point = roundUp(brk_point, PageBytes);
// Set up region for mmaps. For now, start at bottom of kuseg space.
mmap_start = mmap_end = 0x70000000L;
{
Process::initState();
- argsInit(MachineBytes, VMPageSize);
+ argsInit(MachineBytes, PageBytes);
}
void
//XXX Figure out what these should be
auxv.push_back(auxv_t(M5_AT_HWCAP, features));
//The system page size
- auxv.push_back(auxv_t(M5_AT_PAGESZ, PowerISA::VMPageSize));
+ auxv.push_back(auxv_t(M5_AT_PAGESZ, PowerISA::PageBytes));
//Frequency at which times() increments
auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64));
// For statically linked executables, this is the virtual address of the
namespace SparcISA
{
-const int MachineBytes = 8;
-
// This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
// SPARC NOP (sethi %(hi(0), g0)
const MachInst NoopMachInst = 0x01000000;
-// 8K. This value is implmentation specific; and should probably
-// be somewhere else.
-const int LogVMPageSize = 13;
-const int VMPageSize = (1 << LogVMPageSize);
-
// real address virtual mapping
// sort of like alpha super page, but less frequently used
const Addr SegKPMEnd = ULL(0xfffffffc00000000);
const Addr SegKPMBase = ULL(0xfffffac000000000);
-// Why does both the previous set of constants and this one exist?
-const int PageShift = 13;
-const int PageBytes = 1ULL << PageShift;
-
-const int BranchPredAddrShiftAmt = 2;
+const Addr PageShift = 13;
+const Addr PageBytes = ULL(1) << PageShift;
StaticInstPtr decodeInst(ExtMachInst);
// XXX all the below need to be updated for SPARC - Ali
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
- brk_point = roundUp(brk_point, VMPageSize);
+ brk_point = roundUp(brk_point, PageBytes);
// Set pointer for next thread stack. Reserve 8M for main stack.
next_thread_stack_base = stack_base - (8 * 1024 * 1024);
pstate.am = 1;
tc->setMiscReg(MISCREG_PSTATE, pstate);
- argsInit(32 / 8, VMPageSize);
+ argsInit(32 / 8, PageBytes);
}
void
pstate.ie = 1;
tc->setMiscReg(MISCREG_PSTATE, pstate);
- argsInit(sizeof(IntReg), VMPageSize);
+ argsInit(sizeof(IntReg), PageBytes);
}
template<class IntType>
// Bits which describe the system hardware capabilities
auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap));
// The system page size
- auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::VMPageSize));
+ auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::PageBytes));
// Defined to be 100 in the kernel source.
// Frequency at which times() increments
auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
//XXX This needs to be set to an intermediate instruction struct
//which encodes this instruction
- //4k. This value is not constant on x86.
- const int LogVMPageSize = 12;
- const int VMPageSize = (1 << LogVMPageSize);
-
- const int PageShift = 12;
- const int PageBytes = 1ULL << PageShift;
-
- const int BranchPredAddrShiftAmt = 0;
+ const Addr PageShift = 12;
+ const Addr PageBytes = ULL(1) << PageShift;
// Memory accesses can be unaligned
const bool HasUnalignedMemAcc = true;
numSyscallDescs(_numSyscallDescs)
{
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
- brk_point = roundUp(brk_point, VMPageSize);
+ brk_point = roundUp(brk_point, PageBytes);
}
X86_64LiveProcess::X86_64LiveProcess(LiveProcessParams *params,
{
vsyscallPage.base = 0xffffffffff600000ULL;
- vsyscallPage.size = VMPageSize;
+ vsyscallPage.size = PageBytes;
vsyscallPage.vtimeOffset = 0x400;
vsyscallPage.vgettimeofdayOffset = 0x0;
X86LiveProcess(params, objFile, _syscallDescs, _numSyscallDescs)
{
_gdtStart = ULL(0xffffd000);
- _gdtSize = VMPageSize;
+ _gdtSize = PageBytes;
vsyscallPage.base = 0xffffe000ULL;
- vsyscallPage.size = VMPageSize;
+ vsyscallPage.size = PageBytes;
vsyscallPage.vsyscallOffset = 0x400;
vsyscallPage.vsysexitOffset = 0x410;
{
X86LiveProcess::initState();
- argsInit(sizeof(uint64_t), VMPageSize);
+ argsInit(sizeof(uint64_t), PageBytes);
// Set up the vsyscall page for this process.
allocateMem(vsyscallPage.base, vsyscallPage.size);
{
X86LiveProcess::initState();
- argsInit(sizeof(uint32_t), VMPageSize);
+ argsInit(sizeof(uint32_t), PageBytes);
/*
* Set up a GDT for this process. The whole GDT wouldn't really be for
//XXX Figure out what these should be
auxv.push_back(auxv_t(M5_AT_HWCAP, features));
//The system page size
- auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::VMPageSize));
+ auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::PageBytes));
//Frequency at which times() increments
//Defined to be 100 in the kernel source.
auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
process->next_thread_stack_base -= stack_size;
}
- Addr rounded_stack_base = roundDown(stack_base, VMPageSize);
- Addr rounded_stack_size = roundUp(stack_size, VMPageSize);
+ Addr rounded_stack_base = roundDown(stack_base, PageBytes);
+ Addr rounded_stack_size = roundUp(stack_size, PageBytes);
DPRINTF(SyscallVerbose,
"stack_create: allocating stack @ %#x size %#x "
*configptr_ptr = htog(config_addr);
// Register this as a valid address range with the process
- base_addr = roundDown(base_addr, VMPageSize);
+ base_addr = roundDown(base_addr, PageBytes);
int size = cur_addr - base_addr;
- process->allocateMem(base_addr, roundUp(size, VMPageSize));
+ process->allocateMem(base_addr, roundUp(size, PageBytes));
config.copyOut(tc->getMemProxy());
slot_state.copyOut(tc->getMemProxy());
bool
BasePrefetcher::samePage(Addr a, Addr b)
{
- return roundDown(a, TheISA::VMPageSize) == roundDown(b, TheISA::VMPageSize);
+ return roundDown(a, TheISA::PageBytes) == roundDown(b, TheISA::PageBytes);
}
/* setting first level of the page table */
uint64_t log_req_size = floorLog2(sizeof(PageTableEntry)) +
logLevelSize[numLevels-1];
- assert(log_req_size >= LogVMPageSize);
- uint64_t npages = 1 << (log_req_size - LogVMPageSize);
+ assert(log_req_size >= PageShift);
+ uint64_t npages = 1 << (log_req_size - PageShift);
Addr paddr = system->allocPhysPages(npages);
PortProxy &p = system->physProxy;
- p.memsetBlob(paddr, 0, npages << LogVMPageSize);
+ p.memsetBlob(paddr, 0, npages << PageShift);
}
Addr level_base = basePtr;
for (int i = numLevels - 1; i > 0; i--) {
- Addr entry_addr = (level_base<<LogVMPageSize) +
+ Addr entry_addr = (level_base<<PageShift) +
offsets[i] * sizeof(PageTableEntry);
PortProxy &p = system->physProxy;
uint64_t log_req_size = floorLog2(sizeof(PageTableEntry)) +
logLevelSize[i-1];
- assert(log_req_size >= LogVMPageSize);
- uint64_t npages = 1 << (log_req_size - LogVMPageSize);
+ assert(log_req_size >= PageShift);
+ uint64_t npages = 1 << (log_req_size - PageShift);
DPRINTF(MMU, "Allocating %d pages needed for entry in level %d\n", npages, i-1);
/* allocate new entry */
Addr next_entry_paddr = system->allocPhysPages(npages);
- p.memsetBlob(next_entry_paddr, 0, npages << LogVMPageSize);
+ p.memsetBlob(next_entry_paddr, 0, npages << PageShift);
- next_entry_pnum = next_entry_paddr >> LogVMPageSize;
+ next_entry_pnum = next_entry_paddr >> PageShift;
pTableISAOps.setPnum(entry, next_entry_pnum);
pTableISAOps.setPTEFields(entry);
p.write<PageTableEntry>(entry_addr, entry);
level_base = next_entry_pnum;
}
- PTE_addr = (level_base<<LogVMPageSize) +
+ PTE_addr = (level_base<<PageShift) +
offsets[0] * sizeof(PageTableEntry);
DPRINTF(MMU, "Returning PTE_addr: %x\n", PTE_addr);
return true;
PageTableEntry PTE = p.read<PageTableEntry>(PTE_addr);
Addr entry_paddr = pTableISAOps.getPnum(PTE);
if (!clobber && entry_paddr == 0) {
- pTableISAOps.setPnum(PTE, paddr >> LogVMPageSize);
+ pTableISAOps.setPnum(PTE, paddr >> PageShift);
pTableISAOps.setPTEFields(PTE);
p.write<PageTableEntry>(PTE_addr, PTE);
DPRINTF(MMU, "New mapping: %#x-%#x\n", vaddr, paddr);
walk(new_vaddr, true, new_PTE_addr);
PageTableEntry new_PTE = p.read<PageTableEntry>(new_PTE_addr);
- pTableISAOps.setPnum(new_PTE, paddr>>LogVMPageSize);
+ pTableISAOps.setPnum(new_PTE, paddr>>PageShift);
pTableISAOps.setPTEFields(new_PTE);
p.write<PageTableEntry>(new_PTE_addr, new_PTE);
DPRINTF(MMU, "Remapping: %#x-%#x\n", vaddr, new_PTE_addr);
if (pnum == 0)
return false;
- entry = TlbEntry(pid, vaddr, pnum << LogVMPageSize);
+ entry = TlbEntry(pid, vaddr, pnum << PageShift);
updateCache(page_addr, entry);
} else {
return false;
public:
PageTableBase(const std::string &__name, uint64_t _pid,
- Addr _pageSize = TheISA::VMPageSize)
+ Addr _pageSize = TheISA::PageBytes)
: pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
pid(_pid), _name(__name)
{
public:
FuncPageTable(const std::string &__name, uint64_t _pid,
- Addr _pageSize = TheISA::VMPageSize);
+ Addr _pageSize = TheISA::PageBytes);
~FuncPageTable();
{
public:
NoArchPageTable(const std::string &__name, uint64_t _pid, System *_sys,
- Addr _pageSize = TheISA::VMPageSize) : FuncPageTable(__name, _pid)
+ Addr _pageSize = TheISA::PageBytes) : FuncPageTable(__name, _pid)
{
fatal("No architectural page table defined for this ISA.\n");
}
void
Address::makePageAddress()
{
- m_address = maskLowOrderBits(TheISA::LogVMPageSize);
+ m_address = maskLowOrderBits(TheISA::PageShift);
}
Address
{
int prevSize = 0;
- for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
+ for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
Addr paddr;
if (!pTable->translate(gen.addr(),paddr))
{
int prevSize = 0;
- for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
+ for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
Addr paddr;
if (!pTable->translate(gen.addr(), paddr)) {
if (allocating == Always) {
- process->allocateMem(roundDown(gen.addr(), VMPageSize),
- VMPageSize);
+ process->allocateMem(roundDown(gen.addr(), PageBytes),
+ PageBytes);
} else if (allocating == NextPage) {
// check if we've accessed the next page on the stack
if (!process->fixupStackFault(gen.addr()))
bool
SETranslatingPortProxy::tryMemsetBlob(Addr addr, uint8_t val, int size) const
{
- for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
+ for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
Addr paddr;
if (!pTable->translate(gen.addr(), paddr)) {
if (allocating == Always) {
- process->allocateMem(roundDown(gen.addr(), VMPageSize),
- VMPageSize);
+ process->allocateMem(roundDown(gen.addr(), PageBytes),
+ PageBytes);
pTable->translate(gen.addr(), paddr);
} else {
return false;
void
Process::allocateMem(Addr vaddr, int64_t size, bool clobber)
{
- int npages = divCeil(size, (int64_t)VMPageSize);
+ int npages = divCeil(size, (int64_t)PageBytes);
Addr paddr = system->allocPhysPages(npages);
pTable->map(vaddr, paddr, size, clobber);
}
// Check if this is already on the stack and there's just no page there
// yet.
if (vaddr >= stack_min && vaddr < stack_base) {
- allocateMem(roundDown(vaddr, VMPageSize), VMPageSize);
+ allocateMem(roundDown(vaddr, PageBytes), PageBytes);
return true;
}
SyscallReturn
getpagesizeFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc)
{
- return (int)VMPageSize;
+ return (int)PageBytes;
}
if (new_brk > p->brk_point) {
// might need to allocate some new pages
for (ChunkGenerator gen(p->brk_point, new_brk - p->brk_point,
- VMPageSize); !gen.done(); gen.next()) {
+ PageBytes); !gen.done(); gen.next()) {
if (!p->pTable->translate(gen.addr()))
- p->allocateMem(roundDown(gen.addr(), VMPageSize), VMPageSize);
+ p->allocateMem(roundDown(gen.addr(), PageBytes), PageBytes);
// if the address is already there, zero it out
else {
SETranslatingPortProxy &tp = tc->getMemProxy();
// split non-page aligned accesses
- Addr next_page = roundUp(gen.addr(), VMPageSize);
+ Addr next_page = roundUp(gen.addr(), PageBytes);
uint32_t size_needed = next_page - gen.addr();
tp.memsetBlob(gen.addr(), zero, size_needed);
- if (gen.addr() + VMPageSize > next_page &&
+ if (gen.addr() + PageBytes > next_page &&
next_page < new_brk &&
p->pTable->translate(next_page))
{
- size_needed = VMPageSize - size_needed;
+ size_needed = PageBytes - size_needed;
tp.memsetBlob(next_page, zero, size_needed);
}
}
if (use_provided_address)
provided_address = process->getSyscallArg(tc, index);
- if ((start % TheISA::VMPageSize != 0) ||
- (new_length % TheISA::VMPageSize != 0) ||
- (provided_address % TheISA::VMPageSize != 0)) {
+ if ((start % TheISA::PageBytes != 0) ||
+ (new_length % TheISA::PageBytes != 0) ||
+ (provided_address % TheISA::PageBytes != 0)) {
warn("mremap failing: arguments not page aligned");
return -EINVAL;
}
}
}
- if ((start % TheISA::VMPageSize) != 0 ||
- (length % TheISA::VMPageSize) != 0) {
+ if ((start % TheISA::PageBytes) != 0 ||
+ (length % TheISA::PageBytes) != 0) {
warn("mmap failing: arguments not page-aligned: "
"start 0x%x length 0x%x",
start, length);
Addr
System::allocPhysPages(int npages)
{
- Addr return_addr = pagePtr << LogVMPageSize;
+ Addr return_addr = pagePtr << PageShift;
pagePtr += npages;
- if ((pagePtr << LogVMPageSize) > physmem.totalSize())
+ if ((pagePtr << PageShift) > physmem.totalSize())
fatal("Out of memory, please increase size of physical memory.");
return return_addr;
}
Addr
System::freeMemSize() const
{
- return physmem.totalSize() - (pagePtr << LogVMPageSize);
+ return physmem.totalSize() - (pagePtr << PageShift);
}
bool
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