Add new file vr.igen which is a merge of vr5400.igen and vr4320.igen.

Hack sanitize so that it doesn't sanitize vrXXX when either of
keep-vr5400 or keep-vr4320 are specified.
Move two basic vr4100 instructions from mips.igen to vr.igen.

diff --git a/sim/mips/.Sanitize b/sim/mips/.Sanitize
index 7bef23efedf33ec285ab308e18f57c7cb101b8e0..b3b3e93359f398b30c390df696fef0f583f38938 100644 (file)
--- a/sim/mips/.Sanitize
+++ b/sim/mips/.Sanitize
@@ -86,6 +86,7 @@ m16.dc
 m16run.c
 mips.dc
 tx.igen
+vr.igen
 
 Things-to-lose:
 
@@ -212,7 +213,7 @@ else
 fi
 
 
-vr5400_files="ChangeLog configure configure.in sim-main.h interp.c gencode.c mips.igen mips.dc m16.igen vr5400.igen mdmx.igen"
+vr5400_files="ChangeLog configure configure.in sim-main.h interp.c gencode.c mips.igen mips.dc vr5400.igen mdmx.igen vr.igen"
 
 if ( echo $* | grep keep\-vr5400 > /dev/null ) ; then
        for i in $vr5400_files ; do
@@ -241,7 +242,7 @@ else
        done
 fi
 
-vr4320_files="ChangeLog Makefile.in configure configure.in mips.igen"
+vr4320_files="ChangeLog Makefile.in configure configure.in mips.igen vr.igen vr4320.igen"
 
 if ( echo $* | grep keep\-vr4320 > /dev/null ) ; then
        for i in $vr4320_files ; do
@@ -271,6 +272,36 @@ else
 fi
 
 
+vrXXXX_files="vr.igen"
+
+if ( echo $* | grep keep\-vr > /dev/null ) ; then
+       for i in $vrXXXX_files ; do
+               if test ! -d $i && (grep sanitize-vrXXXX $i > /dev/null) ; then
+                       if [ -n "${verbose}" ] ; then
+                               echo Keeping vrXXXX stuff in $i
+                       fi
+               fi
+       done
+else
+       for i in * ; do
+               if test ! -d $i && (grep sanitize-vrXXXX $i > /dev/null) ; then
+                       if [ -n "${verbose}" ] ; then
+                               echo Removing traces of \"vrXXXX\" from $i...
+                       fi
+                       cp $i new
+                       sed '/start\-sanitize\-vrXXXX/,/end-\sanitize\-vrXXXX/d' < $i > new
+                       if [ -n "${safe}" -a ! -f .Recover/$i ] ; then
+                               if [ -n "${verbose}" ] ; then
+                                       echo Caching $i in .Recover...
+                               fi
+                               mv $i .Recover
+                       fi
+                       mv new $i
+               fi
+       done
+fi
+
+
 tx3904_files="ChangeLog configure configure.in interp.c"
 
 if ( echo $* | grep keep\-tx3904 > /dev/null ) ; then

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 4b8f87dcf053c1d3ca014ee768f9033e24657a8c..bedbbdbd77228e80309651d1646b6e2eb9716ce5 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,34 @@
+Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * vr.igen: New file.
+       (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
+       * mips.igen: Define vr4100 model. Include vr.igen.
+       
+start-sanitize-r5900
+Tue Jul 14 16:10:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * r5900.igen (r59fp_overflow): Replace argument ANS with argument
+       SIGN_P.
+       (r59fp_zero): Ditto.
+       (r59fp_store): Update calls.
+       (DIV.S): Compute 0/0 sign from inputs. Ditto for X/0.
+
+end-sanitize-r5900
+start-sanitize-branchbug4011
+Mon Jun 29 09:31:27 1998  Gavin Koch  <gavin@cygnus.com>
+
+       * interp.c (OPTION_BRANCH_BUG_4011): Add.
+       (mips_option_handler): Handle OPTION_BRANCH_BUG_4011.
+       (mips_options): Define the option.
+       * mips.igen (check_4011_branch_bug): New.
+       (mark_4011_branch_bug): New.
+       (all branch insn): Call mark_branch_bug, and check_branch_bug.
+       * sim-main.h (branchbug4011_option, branchbug4011_last_target, 
+       branchbug4011_last_cia, BRANCHBUG4011_OPTION, 
+       BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA,
+       check_branch_bug, mark_branch_bug): Define.
+
+end-sanitize-branchbug4011
 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 
        * mips.igen (check_mf_hilo): Correct check.

diff --git a/sim/mips/vr.igen b/sim/mips/vr.igen
new file mode 100644 (file)
index 0000000..e2118e9
--- /dev/null
+++ b/sim/mips/vr.igen
@@ -0,0 +1,491 @@
+// -*- C -*-
+//
+// NEC specific instructions
+//
+
+// Integer Instructions
+// --------------------
+//
+// MulAcc is the Multiply Accumulator.
+//     This register is mapped on the the HI and LO registers.
+//     Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
+//     Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
+
+
+:function:::unsigned64:MulAcc:
+{
+  unsigned64 result = U8_4 (HI, LO);
+  return result;
+}
+
+:function:::void:SET_MulAcc:unsigned64 value
+{
+  *AL4_8 (&HI) = VH4_8 (value);
+  *AL4_8 (&LO) = VL4_8 (value);
+}
+
+:function:::signed64:SignedMultiply:signed32 l, signed32 r
+{
+  signed64 result = (signed64) l * (signed64) r;
+  return result;
+}
+
+:function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
+{
+  unsigned64 result = (unsigned64) l * (unsigned64) r;
+  return result;
+}
+
+:function:::unsigned64:Low32Bits:unsigned64 value
+{
+  unsigned64 result = (signed64) (signed32) VL4_8 (value);
+  return result;
+}
+
+:function:::unsigned64:High32Bits:unsigned64 value
+{
+  unsigned64 result = (signed64) (signed32) VH4_8 (value);
+  return result;
+}
+
+
+
+// Multiply, Accumulate
+000000,5.RS,5.RT,00000,00000,101000::::MAC
+"mac r<RS>, r<RT>"
+*vr4100:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+{
+  SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
+}
+
+
+// D-Multiply, Accumulate
+000000,5.RS,5.RT,00000,00000,101001::::DMAC
+"dmac r<RS>, r<RT>"
+*vr4100:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+{
+  LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
+}
+
+
+// start-sanitize-vr4320
+// Count Leading Zeros
+000000,5.RS,00000,5.RD,00000,110101::::CLZ
+"clz r<RD>, r<RS>"
+// end-sanitize-vr4320
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitize-vr4320
+{
+  unsigned32 t = Low32Bits (SD_, GPR[RS]);
+  signed64 c = 0;
+
+  while (! (t & ( 1 << 31))
+       && c < 32)
+    {
+    c++;
+    t <<= 1;
+    }
+
+  GPR[RD] = c;
+}
+
+
+// end-sanitize-vr4320
+// start-sanitize-vr4320
+// D-Count Leading Zeros
+000000,5.RS,00000,5.RD,00000,111101::::DCLZ
+"dclz r<RD>, r<RS>"
+// end-sanitize-vr4320
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitize-vr4320
+{
+  unsigned64 t = GPR[RS];
+  signed64 c = 0;
+
+  while (! (t & ( (unsigned64)1 << 63))
+       && c < 64)
+    {
+    c++;
+    t <<= 1;
+    }
+
+  printf("lo %d\n", (int) c);
+  GPR[RD] = c;
+}
+
+
+
+
+
+
+
+// end-sanitize-vr4320
+// start-sanitize-vrXXXX
+// Multiply and Move LO.
+000000,5.RS,5.RT,5.RD,00100,101000::::MUL
+"mul r<RD>, r<RS>, r<RT>"
+// end-sanitize-vrXXXX
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitze-vr5400
+*vr5400:
+// end-sanitze-vr5400
+// start-sanitize-vrXXXX
+{
+  SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
+}
+
+
+// end-sanitize-vrXXXX
+// start-sanitize-vrXXXX
+// Unsigned Multiply and Move LO.
+000000,5.RS,5.RT,5.RD,00101,101000::::MULU
+"mulu r<RD>, r<RS>, r<RT>"
+// end-sanitize-vrXXXX
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitze-vr5400
+*vr5400:
+// end-sanitze-vr5400
+// start-sanitize-vrXXXX
+{
+  SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
+}
+
+
+// end-sanitize-vrXXXX
+// start-sanitize-vrXXXX
+// Multiply and Move HI.
+000000,5.RS,5.RT,5.RD,01100,101000::::MULHI
+"mulhi r<RD>, r<RS>, r<RT>"
+// end-sanitize-vrXXXX
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitze-vr5400
+*vr5400:
+// end-sanitze-vr5400
+// start-sanitize-vrXXXX
+{
+  SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+}
+
+
+// end-sanitize-vrXXXX
+// start-sanitize-vrXXXX
+// Unsigned Multiply and Move HI.
+000000,5.RS,5.RT,5.RD,01101,101000::::MULHIU
+"mulhiu r<RD>, r<RS>, r<RT>"
+// end-sanitize-vrXXXX
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitze-vr5400
+*vr5400:
+// end-sanitze-vr5400
+// start-sanitize-vrXXXX
+{
+  SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+}
+
+
+// end-sanitize-vrXXXX
+// start-sanitze-vr5400
+// Multiply, Negate and Move LO.
+000000,5.RS,5.RT,5.RD,00011,011000::::MULS
+"muls r<RD>, r<RS>, r<RT>"
+// end-sanitze-vr5400
+// start-sanitze-vr5400
+*vr5400:
+// end-sanitze-vr5400
+// start-sanitze-vr5400
+{
+  SET_MulAcc (SD_, 0 - SignedMultiply   (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
+}
+
+
+// end-sanitze-vr5400
+// start-sanitze-vr5400
+// Unsigned Multiply, Negate and Move LO.
+000000,5.RS,5.RT,5.RD,00011,011001::::MULSU
+"mulsu r<RD>, r<RS>, r<RT>"
+// end-sanitze-vr5400
+// start-sanitze-vr5400
+*vr5400:
+// end-sanitze-vr5400
+// start-sanitze-vr5400
+{
+  SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
+}
+
+
+// end-sanitze-vr5400
+// start-sanitze-vr5400
+// Multiply, Negate and Move HI.
+000000,5.RS,5.RT,5.RD,01011,011000::::MULSHI
+"mulshi r<RD>, r<RS>, r<RT>"
+// end-sanitze-vr5400
+// start-sanitze-vr5400
+*vr5400:
+// end-sanitze-vr5400
+// start-sanitze-vr5400
+{
+  SET_MulAcc (SD_, 0 - SignedMultiply   (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+}
+
+
+// end-sanitze-vr5400
+// start-sanitze-vr5400
+// Unsigned Multiply, Negate and Move HI.
+000000,5.RS,5.RT,5.RD,01011,011001::::MULSHIU
+"mulshiu r<RD>, r<RS>, r<RT>"
+// end-sanitze-vr5400
+// start-sanitze-vr5400
+*vr5400:
+// end-sanitze-vr5400
+// start-sanitze-vr5400
+{
+  SET_MulAcc (SD_, 0 - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+}
+
+
+
+
+
+// end-sanitze-vr5400
+// Multiply, Accumulate and Move LO.
+000000,5.RS,5.RT,5.RD,00010,101000::::MACC
+"macc r<RD>, r<RS>, r<RT>"
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitze-vr5400
+*vr5400:
+// end-sanitze-vr5400
+{
+  SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
+}
+
+
+// end-sanitize-vr4320
+// start-sanitize-vrXXXX
+// Unsigned Multiply, Accumulate and Move LO.
+000000,5.RS,5.RT,5.RD,00011,101000::::MACCU
+"maccu r<RD>, r<RS>, r<RT>"
+// end-sanitize-vrXXXX
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitze-vr5400
+*vr5400:
+// end-sanitze-vr5400
+// start-sanitize-vrXXXX
+{
+  SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
+}
+
+
+// end-sanitize-vrXXXX
+// start-sanitize-vrXXXX
+// Multiply, Accumulate and Move HI.
+000000,5.RS,5.RT,5.RD,01010,101000::::MACCHI
+"macchi r<RD>, r<RS>, r<RT>"
+// end-sanitize-vrXXXX
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitze-vr5400
+*vr5400:
+// end-sanitze-vr5400
+// start-sanitize-vrXXXX
+{
+  SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+}
+
+
+// end-sanitize-vrXXXX
+// start-sanitize-vrXXXX
+// Unsigned Multiply, Accumulate and Move HI.
+000000,5.RS,5.RT,5.RD,01011,101000::::MACCHIU
+"macchiu r<RD>, r<RS>, r<RT>"
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitze-vr5400
+*vr5400:
+// end-sanitze-vr5400
+{
+  SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+
+}
+
+
+
+// end-sanitize-vrXXXX
+// start-sanitize-vr5400
+// Multiply, Negate, Accumulate and Move LO.
+000000,5.RS,5.RT,5.RD,00111,011000::::MSAC
+"msac r<RD>, r<RS>, r<RT>"
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+{
+  SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
+}
+
+
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+// Unsigned Multiply, Negate, Accumulate and Move LO.
+000000,5.RS,5.RT,5.RD,00111,011001::::MSACU
+"msacu r<RD>, r<RS>, r<RT>"
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+{
+  SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = Low32Bits  (SD_, MulAcc (SD_));
+}
+
+
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+// Multiply, Negate, Accumulate and Move HI.
+000000,5.RS,5.RT,5.RD,01111,011000::::MSACHI
+"msachi r<RD>, r<RS>, r<RT>"
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+{
+  SET_MulAcc (SD_, MulAcc (SD_) - SignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+}
+
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+// Unsigned Multiply, Negate, Accumulate and Move HI.
+000000,5.RS,5.RT,5.RD,01111,011001::::MSACHIU
+"msachiu r<RD>, r<RS>, r<RT>"
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+{
+  SET_MulAcc (SD_, MulAcc (SD_) - UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
+  GPR[RD] = High32Bits (SD_, MulAcc (SD_));
+}
+
+
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+// Rotate Right.
+000000,00001,5.RT,5.RD,5.SHIFT,000010::::ROR
+"ror r<RD>, r<RT>, <SHIFT>"
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+{
+  int s = SHIFT;
+  GPR[RD] = ROTR32 (GPR[RT], s);
+}
+
+
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+// Rotate Right Variable.
+000000,5.RS,5.RT,5.RD,00001,000110::::RORV
+"rorv r<RD>, r<RT>, <RS>"
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+{
+  int s = MASKED (GPR[RS], 4, 0);
+  GPR[RD] = ROTR32 (GPR[RT], s);
+}
+
+
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+// Double Rotate Right.
+000000,00001,5.RT,5.RD,5.SHIFT,111010::::DROR
+"dror r<RD>, r<RT>, <SHIFT>"
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+{
+  int s = SHIFT;
+  GPR[RD] = ROTR64 (GPR[RT], s);
+}
+
+
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+// Double Rotate Right Plus 32.
+000000,00001,5.RT,5.RD,5.SHIFT,111110::::DROR32
+"dror32 r<RD>, r<RT>, <SHIFT>"
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+{
+  int s = SHIFT + 32;
+  GPR[RD] = ROTR64 (GPR[RT], s);
+}
+
+
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+// Double Rotate Right Variable.
+000000,5.RS,5.RT,5.RD,00001,010110::::DRORV
+"drorv r<RD>, r<RT>, <RS>"
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+// start-sanitize-vr5400
+{
+  int s = MASKED (GPR[RS], 5, 0);
+  GPR[RD] = ROTR64 (GPR[RT], s);
+}
+
+
+// end-sanitize-vr5400