i965: Document which instructions are generation specific.

Signed-off-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index a962c7b7787429d17d313dc8e4fc6faa10028d63..1a9119c43f492c2993ec668cec0074411481d25c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -717,15 +717,15 @@ enum opcode {
    BRW_OPCODE_ASR =    12,
    BRW_OPCODE_CMP =    16,
    BRW_OPCODE_CMPN =   17,
-   BRW_OPCODE_F32TO16 = 19,
-   BRW_OPCODE_F16TO32 = 20,
-   BRW_OPCODE_BFREV =  23,
-   BRW_OPCODE_BFE =    24,
-   BRW_OPCODE_BFI1 =   25,
-   BRW_OPCODE_BFI2 =   26,
+   BRW_OPCODE_F32TO16 = 19,  /**< Gen7 only */
+   BRW_OPCODE_F16TO32 = 20,  /**< Gen7 only */
+   BRW_OPCODE_BFREV =  23,  /**< Gen7+ */
+   BRW_OPCODE_BFE =    24,  /**< Gen7+ */
+   BRW_OPCODE_BFI1 =   25,  /**< Gen7+ */
+   BRW_OPCODE_BFI2 =   26,  /**< Gen7+ */
    BRW_OPCODE_JMPI =   32,
    BRW_OPCODE_IF =     34,
-   BRW_OPCODE_IFF =    35,
+   BRW_OPCODE_IFF =    35,  /**< Pre-Gen6 */
    BRW_OPCODE_ELSE =   36,
    BRW_OPCODE_ENDIF =  37,
    BRW_OPCODE_DO =     38,
@@ -733,14 +733,14 @@ enum opcode {
    BRW_OPCODE_BREAK =  40,
    BRW_OPCODE_CONTINUE = 41,
    BRW_OPCODE_HALT =   42,
-   BRW_OPCODE_MSAVE =  44,
-   BRW_OPCODE_MRESTORE = 45,
-   BRW_OPCODE_PUSH =   46,
-   BRW_OPCODE_POP =    47,
+   BRW_OPCODE_MSAVE =  44,  /**< Pre-Gen6 */
+   BRW_OPCODE_MRESTORE = 45, /**< Pre-Gen6 */
+   BRW_OPCODE_PUSH =   46,  /**< Pre-Gen6 */
+   BRW_OPCODE_POP =    47,  /**< Pre-Gen6 */
    BRW_OPCODE_WAIT =   48,
    BRW_OPCODE_SEND =   49,
    BRW_OPCODE_SENDC =  50,
-   BRW_OPCODE_MATH =   56,
+   BRW_OPCODE_MATH =   56,  /**< Gen6+ */
    BRW_OPCODE_ADD =    64,
    BRW_OPCODE_MUL =    65,
    BRW_OPCODE_AVG =    66,
@@ -752,11 +752,11 @@ enum opcode {
    BRW_OPCODE_MAC =    72,
    BRW_OPCODE_MACH =   73,
    BRW_OPCODE_LZD =    74,
-   BRW_OPCODE_FBH =    75,
-   BRW_OPCODE_FBL =    76,
-   BRW_OPCODE_CBIT =   77,
-   BRW_OPCODE_ADDC =   78,
-   BRW_OPCODE_SUBB =   79,
+   BRW_OPCODE_FBH =    75,  /**< Gen7+ */
+   BRW_OPCODE_FBL =    76,  /**< Gen7+ */
+   BRW_OPCODE_CBIT =   77,  /**< Gen7+ */
+   BRW_OPCODE_ADDC =   78,  /**< Gen7+ */
+   BRW_OPCODE_SUBB =   79,  /**< Gen7+ */
    BRW_OPCODE_SAD2 =   80,
    BRW_OPCODE_SADA2 =  81,
    BRW_OPCODE_DP4 =    84,
@@ -764,9 +764,9 @@ enum opcode {
    BRW_OPCODE_DP3 =    86,
    BRW_OPCODE_DP2 =    87,
    BRW_OPCODE_LINE =   89,
-   BRW_OPCODE_PLN =    90,
-   BRW_OPCODE_MAD =    91,
-   BRW_OPCODE_LRP =    92,
+   BRW_OPCODE_PLN =    90,  /**< G45+ */
+   BRW_OPCODE_MAD =    91,  /**< Gen6+ */
+   BRW_OPCODE_LRP =    92,  /**< Gen6+ */
    BRW_OPCODE_NOP =    126,
 
    /* These are compiler backend opcodes that get translated into other