SCons: Support building without an ISA

diff --git a/build_opts/NOISA b/build_opts/NOISA
new file mode 100644 (file)
index 0000000..dd1f82a
--- /dev/null
+++ b/build_opts/NOISA
@@ -0,0 +1,2 @@
+TARGET_ISA = 'no'
+CPU_MODELS = 'no'

diff --git a/src/arch/noisa/SConsopts b/src/arch/noisa/SConsopts
new file mode 100644 (file)
index 0000000..fbfcf05
--- /dev/null
+++ b/src/arch/noisa/SConsopts
@@ -0,0 +1,4 @@
+
+Import('*')
+
+all_isa_list.append('no')

diff --git a/src/arch/noisa/cpu_dummy.hh b/src/arch/noisa/cpu_dummy.hh
new file mode 100644 (file)
index 0000000..2b83f5e
--- /dev/null
+++ b/src/arch/noisa/cpu_dummy.hh
@@ -0,0 +1,6 @@
+
+class BaseCPU
+{
+  public:
+    static int numSimulatedInstructions() { return 0; }
+};

diff --git a/src/base/SConscript b/src/base/SConscript
index 9ddeb8705e64e16b33c0d16628db3e55b9b4f1c8..91671f817f0d78ed42c770700736eb98b4f21318 100644 (file)
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -56,7 +56,8 @@ Source('pollevent.cc')
 Source('random.cc')
 Source('random_mt.cc')
 Source('range.cc')
-Source('remote_gdb.cc')
+if env['TARGET_ISA'] != 'no':
+    Source('remote_gdb.cc')
 Source('sat_counter.cc')
 Source('socket.cc')
 Source('statistics.cc')

diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 35e92a1b69ca17284836877760a954147a1ac351..99308c2fb4522273a8c35ec7cbddc7a10c0373b4 100644 (file)
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 #################################################################
 #
 # Generate StaticInst execute() method signatures.

diff --git a/src/cpu/nocpu/SConsopts b/src/cpu/nocpu/SConsopts
new file mode 100644 (file)
index 0000000..0baef0a
--- /dev/null
+++ b/src/cpu/nocpu/SConsopts
@@ -0,0 +1,4 @@
+
+Import('*')
+
+CpuModel('no', '', '', { '': '' })

diff --git a/src/dev/SConscript b/src/dev/SConscript
index c09ec3dcdd8df7984e060179538e9a1f7676da11..7cdea7961fea5d40b2e4ddd7aeaa35e7c8724f43 100644 (file)
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -31,6 +31,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 if env['FULL_SYSTEM']:
     SimObject('BadDevice.py')
     SimObject('CopyEngine.py')

diff --git a/src/kern/SConscript b/src/kern/SConscript
index fc682aee012ff776feb249a5a276968b641b19d3..145f0d98697cc86357be4fd5cf6f9a4db868cdde 100644 (file)
--- a/src/kern/SConscript
+++ b/src/kern/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 if env['FULL_SYSTEM']:
     Source('kernel_stats.cc')
     Source('system_events.cc')

diff --git a/src/mem/SConscript b/src/mem/SConscript
index 46de3eb578ec5cc58d836d32f6454c9d56bb2afe..52c5307321a3b80c38f77bbbd304db2e8abb268f 100644 (file)
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -33,21 +33,23 @@ Import('*')
 SimObject('Bridge.py')
 SimObject('Bus.py')
 SimObject('MemObject.py')
-SimObject('PhysicalMemory.py')
 
 Source('bridge.cc')
 Source('bus.cc')
-Source('dram.cc')
 Source('mem_object.cc')
 Source('packet.cc')
-Source('physical.cc')
 Source('port.cc')
 Source('tport.cc')
 Source('mport.cc')
 
+if env['TARGET_ISA'] != 'no':
+    SimObject('PhysicalMemory.py')
+    Source('dram.cc')
+    Source('physical.cc')
+
 if env['FULL_SYSTEM']:
     Source('vport.cc')
-else:
+elif env['TARGET_ISA'] != 'no':
     Source('page_table.cc')
     Source('translating_port.cc')
 

diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index 3b8bdb0c839776473b36766e54724bb0f93f7d93..781521d3f1f6cd30ccb47af45767cd0e5fdf20df 100644 (file)
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 SimObject('BaseCache.py')
 
 Source('base.cc')

diff --git a/src/mem/cache/prefetch/SConscript b/src/mem/cache/prefetch/SConscript
index 7314b5ccff344a06130bddc88bf9a5e87978321f..9d05a8ee4fa27ecdae1cdb180ab06c7821a084c3 100644 (file)
--- a/src/mem/cache/prefetch/SConscript
+++ b/src/mem/cache/prefetch/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 Source('base.cc')
 Source('ghb.cc')
 Source('stride.cc')

diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index 37ed5dc85aa24c8e403a044047e32a747ca13ed2..d640a9f13080931910703f7737df980fdf273b7e 100644 (file)
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 Source('base.cc')
 Source('fa_lru.cc')
 Source('iic.cc')

diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript
index 1f7509df4955033dd4dab0010697214a5614e550..339787a222027797c8293a2ae72391401e4100d2 100644 (file)
--- a/src/mem/ruby/SConscript
+++ b/src/mem/ruby/SConscript
@@ -37,6 +37,9 @@ import SCons
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 if not env['RUBY']:
     Return()
 

diff --git a/src/python/swig/pyobject.hh b/src/python/swig/pyobject.hh
index b18a2a76c1b44a976e1aa951d0ff078e1b76389c..ab22df864f6a3264b143b38a7239709e598f67ef 100644 (file)
--- a/src/python/swig/pyobject.hh
+++ b/src/python/swig/pyobject.hh
@@ -31,10 +31,8 @@
 #include <Python.h>
 
 #include "base/types.hh"
-#include "cpu/base.hh"
 #include "sim/serialize.hh"
 #include "sim/sim_object.hh"
-#include "sim/system.hh"
 
 extern "C" SimObject *convertSwigSimObjectPtr(PyObject *);
 SimObject *resolveSimObject(const std::string &name);

diff --git a/src/sim/SConscript b/src/sim/SConscript
index b1e3a4b022743691b969b40208b13882ce6f3888..97c6ddaaea927913e2af943f55d785c152dc60b3 100644 (file)
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -32,28 +32,30 @@ Import('*')
 
 SimObject('BaseTLB.py')
 SimObject('Root.py')
-SimObject('System.py')
 SimObject('InstTracer.py')
 
 Source('async.cc')
 Source('core.cc')
 Source('debug.cc')
 Source('eventq.cc')
-Source('faults.cc')
 Source('init.cc')
 Source('main.cc', bin_only=True)
-Source('pseudo_inst.cc')
 Source('root.cc')
 Source('serialize.cc')
 Source('sim_events.cc')
 Source('sim_object.cc')
 Source('simulate.cc')
 Source('stat_control.cc')
-Source('system.cc')
+
+if env['TARGET_ISA'] != 'no':
+    SimObject('System.py')
+    Source('faults.cc')
+    Source('pseudo_inst.cc')
+    Source('system.cc')
 
 if env['FULL_SYSTEM']:
     Source('arguments.cc')
-else:
+elif env['TARGET_ISA'] != 'no':
     Source('tlb.cc')
     SimObject('Process.py')
 

diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc
index 373a3f2973f2eb7df47620f5ebdb2e466aee846d..07e1b2380e1d917294cff4835d9450b3ddb16812 100644 (file)
--- a/src/sim/stat_control.cc
+++ b/src/sim/stat_control.cc
@@ -39,7 +39,14 @@
 #include "base/hostinfo.hh"
 #include "base/statistics.hh"
 #include "base/time.hh"
+
+#include "config/the_isa.hh"
+#if THE_ISA == NO_ISA
+#include "arch/noisa/cpu_dummy.hh"
+#else
 #include "cpu/base.hh"
+#endif
+
 #include "sim/eventq.hh"
 
 using namespace std;

diff --git a/src/unittest/SConscript b/src/unittest/SConscript
index 1c1959165f75f2d8cd784785c14233ef008a93ff..91ead522f9e13dd1fd276bcca4fd4cb1e6a32bfb 100644 (file)
--- a/src/unittest/SConscript
+++ b/src/unittest/SConscript
@@ -30,6 +30,9 @@
 
 Import('*')
 
+if env['TARGET_ISA'] == 'no':
+    Return()
+
 UnitTest('bitvectest', 'bitvectest.cc')
 UnitTest('circletest', 'circletest.cc')
 UnitTest('cprintftest', 'cprintftest.cc')