Reset TB and DECR
authorAnton Blanchard <anton@linux.ibm.com>
Sun, 3 Jan 2021 05:07:46 +0000 (16:07 +1100)
committerAnton Blanchard <anton@ozlabs.org>
Sun, 3 Jan 2021 05:07:46 +0000 (16:07 +1100)
We don't care what the values of TB and DECR are after reset, but we
don't want the X state to propagate to other parts of the chip.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
execute1.vhdl

index 4f85f3d1f874de92cbdc4eb924eda27792c0e57a..f9b46c1a62e9db2c07835280bfb2cfba4e5c4bf3 100644 (file)
@@ -282,6 +282,8 @@ begin
        if rising_edge(clk) then
             if rst = '1' then
                 r <= reg_type_init;
+                ctrl.tb <= (others => '0');
+                ctrl.dec <= (others => '0');
                 ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
                 ctrl.irq_state <= WRITE_SRR0;
             else