It's a remnant of some old NV extension. Unused.
I also have a patch that removes predicates if anyone is interested.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
/*
* Saturate the value
*/
-
- switch (inst->Instruction.Saturate) {
- case TGSI_SAT_NONE:
- break;
-
- case TGSI_SAT_ZERO_ONE:
+ if (inst->Instruction.Saturate) {
value = lp_build_max(&bld->bld_base.base, value, bld->bld_base.base.zero);
value = lp_build_min(&bld->bld_base.base, value, bld->bld_base.base.one);
- break;
-
- case TGSI_SAT_MINUS_PLUS_ONE:
- value = lp_build_max(&bld->bld_base.base, value, lp_build_const_vec(bld->bld_base.base.gallivm, bld->bld_base.base.type, -1.0));
- value = lp_build_min(&bld->bld_base.base, value, bld->bld_base.base.one);
- break;
-
- default:
- assert(0);
}
/*
*
* It is always assumed to be float.
*/
- switch( inst->Instruction.Saturate ) {
- case TGSI_SAT_NONE:
- break;
-
- case TGSI_SAT_ZERO_ONE:
+ if (inst->Instruction.Saturate) {
assert(dtype == TGSI_TYPE_FLOAT ||
dtype == TGSI_TYPE_UNTYPED);
value = LLVMBuildBitCast(builder, value, float_bld->vec_type, "");
value = lp_build_clamp_zero_one_nanzero(float_bld, value);
- break;
-
- case TGSI_SAT_MINUS_PLUS_ONE:
- assert(dtype == TGSI_TYPE_FLOAT ||
- dtype == TGSI_TYPE_UNTYPED);
- value = LLVMBuildBitCast(builder, value, float_bld->vec_type, "");
- /* This will give -1.0 for NaN which is probably not what we want. */
- value = lp_build_max_ext(float_bld, value,
- lp_build_const_vec(gallivm, float_bld->type, -1.0),
- GALLIVM_NAN_RETURN_OTHER_SECOND_NONNAN);
- value = lp_build_min(float_bld, value, float_bld->one);
- break;
-
- default:
- assert(0);
}
if (reg->Register.Indirect) {
}
if (tgsi_inst->Instruction.Saturate) {
- assert(tgsi_inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
assert(!dest.dest.is_ssa);
ttn_move_dest(b, dest, nir_fsat(b, ttn_src_for_dest(b, &dest)));
}
instruction.Type = TGSI_TOKEN_TYPE_INSTRUCTION;
instruction.NrTokens = 0;
instruction.Opcode = TGSI_OPCODE_MOV;
- instruction.Saturate = TGSI_SAT_NONE;
+ instruction.Saturate = 0;
instruction.Predicate = 0;
instruction.NumDstRegs = 1;
instruction.NumSrcRegs = 1;
struct tgsi_instruction instruction;
assert (opcode <= TGSI_OPCODE_LAST);
- assert (saturate <= TGSI_SAT_MINUS_PLUS_ONE);
+ assert (saturate <= 1);
assert (num_dst_regs <= 3);
assert (num_src_regs <= 15);
TXT( info->mnemonic );
- switch (inst->Instruction.Saturate) {
- case TGSI_SAT_NONE:
- break;
- case TGSI_SAT_ZERO_ONE:
+ if (inst->Instruction.Saturate) {
TXT( "_SAT" );
- break;
- case TGSI_SAT_MINUS_PLUS_ONE:
- TXT( "_SATNV" );
- break;
- default:
- assert( 0 );
}
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
if (!dst)
return;
- switch (inst->Instruction.Saturate) {
- case TGSI_SAT_NONE:
+ if (!inst->Instruction.Saturate) {
for (i = 0; i < TGSI_QUAD_SIZE; i++)
if (execmask & (1 << i))
dst->i[i] = chan->i[i];
- break;
-
- case TGSI_SAT_ZERO_ONE:
+ }
+ else {
for (i = 0; i < TGSI_QUAD_SIZE; i++)
if (execmask & (1 << i)) {
if (chan->f[i] < 0.0f)
else
dst->i[i] = chan->i[i];
}
- break;
-
- case TGSI_SAT_MINUS_PLUS_ONE:
- for (i = 0; i < TGSI_QUAD_SIZE; i++)
- if (execmask & (1 << i)) {
- if (chan->f[i] < -1.0f)
- dst->f[i] = -1.0f;
- else if (chan->f[i] > 1.0f)
- dst->f[i] = 1.0f;
- else
- dst->i[i] = chan->i[i];
- }
- break;
-
- default:
- assert( 0 );
}
}
union tgsi_double_channel temp;
const uint execmask = mach->ExecMask;
- switch (inst->Instruction.Saturate) {
- case TGSI_SAT_NONE:
+ if (!inst->Instruction.Saturate) {
for (i = 0; i < TGSI_QUAD_SIZE; i++)
if (execmask & (1 << i)) {
dst[0].u[i] = chan->u[i][0];
dst[1].u[i] = chan->u[i][1];
}
- break;
-
- case TGSI_SAT_ZERO_ONE:
+ }
+ else {
for (i = 0; i < TGSI_QUAD_SIZE; i++)
if (execmask & (1 << i)) {
if (chan->d[i] < 0.0)
dst[0].u[i] = temp.u[i][0];
dst[1].u[i] = temp.u[i][1];
}
- break;
-
- case TGSI_SAT_MINUS_PLUS_ONE:
- for (i = 0; i < TGSI_QUAD_SIZE; i++)
- if (execmask & (1 << i)) {
- if (chan->d[i] < -1.0)
- temp.d[i] = -1.0;
- else if (chan->d[i] > 1.0)
- temp.d[i] = 1.0;
- else
- temp.d[i] = chan->d[i];
-
- dst[0].u[i] = temp.u[i][0];
- dst[1].u[i] = temp.u[i][1];
- }
- break;
-
- default:
- assert( 0 );
}
store_dest_double(mach, &dst[0], reg, inst, chan_0, TGSI_EXEC_DATA_UINT);
/* MOV_SAT tmpA.<mask>, tmpA */
if (mask) {
- create_mov(tctx, &ctx->tmp[A].dst, &ctx->tmp[A].src, mask,
- TGSI_SAT_ZERO_ONE);
+ create_mov(tctx, &ctx->tmp[A].dst, &ctx->tmp[A].src, mask, 1);
}
/* modify the texture samp instruction to take fixed up coord: */
/* simple case: the whole string matches the instruction name */
if (str_match_nocase_whole(&cur, info->mnemonic)) {
*pcur = cur;
- *saturate = TGSI_SAT_NONE;
+ *saturate = 0;
return TRUE;
}
/* the instruction has a suffix, figure it out */
if (str_match_nocase_whole(&cur, "_SAT")) {
*pcur = cur;
- *saturate = TGSI_SAT_ZERO_ONE;
- return TRUE;
- }
-
- if (str_match_nocase_whole(&cur, "_SATNV")) {
- *pcur = cur;
- *saturate = TGSI_SAT_MINUS_PLUS_ONE;
+ *saturate = 1;
return TRUE;
}
}
boolean has_label )
{
uint i;
- uint saturate = TGSI_SAT_NONE;
+ uint saturate = 0;
const struct tgsi_opcode_info *info;
struct tgsi_full_instruction inst;
const char *cur;
static void
add_vector_clamp(struct tgsi_full_instruction *inst, struct ir2_instruction *alu)
{
- switch (inst->Instruction.Saturate) {
- case TGSI_SAT_NONE:
- break;
- case TGSI_SAT_ZERO_ONE:
+ if (inst->Instruction.Saturate) {
alu->alu.vector_clamp = true;
- break;
- case TGSI_SAT_MINUS_PLUS_ONE:
- DBG("unsupported saturate");
- assert(0);
- break;
}
}
static void
add_scalar_clamp(struct tgsi_full_instruction *inst, struct ir2_instruction *alu)
{
- switch (inst->Instruction.Saturate) {
- case TGSI_SAT_NONE:
- break;
- case TGSI_SAT_ZERO_ONE:
+ if (inst->Instruction.Saturate) {
alu->alu.scalar_clamp = true;
- break;
- case TGSI_SAT_MINUS_PLUS_ONE:
- DBG("unsupported saturate");
- assert(0);
- break;
}
}
struct tgsi_src_register tmp_src;
const struct tgsi_src_register *coord;
bool using_temp = (inst->Dst[0].Register.File == TGSI_FILE_OUTPUT) ||
- (inst->Instruction.Saturate != TGSI_SAT_NONE);
+ inst->Instruction.Saturate;
int idx;
if (using_temp || (opc == TGSI_OPCODE_TXP))
tgsi_get_opcode_name(opc));
}
- switch (inst->Instruction.Saturate) {
- case TGSI_SAT_ZERO_ONE:
+ if (inst->Instruction.Saturate) {
create_clamp_imm(ctx, &inst->Dst[0].Register,
fui(0.0), fui(1.0));
- break;
- case TGSI_SAT_MINUS_PLUS_ONE:
- create_clamp_imm(ctx, &inst->Dst[0].Register,
- fui(-1.0), fui(1.0));
- break;
}
instr_finish(ctx);
if ( current.Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION &&
current.FullInstruction.Instruction.Opcode == TGSI_OPCODE_MOV &&
op_has_dst(current.FullInstruction.Instruction.Opcode) &&
- current.FullInstruction.Instruction.Saturate == TGSI_SAT_NONE &&
+ !current.FullInstruction.Instruction.Saturate &&
current.FullInstruction.Src[0].Register.Absolute == 0 &&
current.FullInstruction.Src[0].Register.Negate == 0 &&
is_unswizzled(¤t.FullInstruction.Src[0], current.FullInstruction.Dst[0].Register.WriteMask) &&
next->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION &&
next->FullInstruction.Instruction.Opcode == TGSI_OPCODE_MOV &&
op_has_dst(current->FullInstruction.Instruction.Opcode) &&
- next->FullInstruction.Instruction.Saturate == TGSI_SAT_NONE &&
+ !next->FullInstruction.Instruction.Saturate &&
next->FullInstruction.Src[0].Register.Absolute == 0 &&
next->FullInstruction.Src[0].Register.Negate == 0 &&
unused_from(ctx, ¤t->FullInstruction.Dst[0], index) &&
= inst->Dst[0].Register.WriteMask;
uint flags = 0x0;
- if (inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE)
+ if (inst->Instruction.Saturate)
flags |= A0_DEST_SATURATE;
if (writeMask & TGSI_WRITEMASK_X)
if (!dst_is_scratch[i])
continue;
- if (tgsi_inst->Instruction.Saturate == TGSI_SAT_MINUS_PLUS_ONE)
- tc_fail(tgsi->tc, "TGSI_SAT_MINUS_PLUS_ONE unhandled");
-
tgsi->tc->templ.saturate = tgsi_inst->Instruction.Saturate;
/* emit indirect store */
{
const tgsi::Instruction::DstRegister dst = tgsi.getDst(d);
- switch (tgsi.getSaturate()) {
- case TGSI_SAT_NONE:
- break;
- case TGSI_SAT_ZERO_ONE:
+ if (tgsi.getSaturate()) {
mkOp1(OP_SAT, dstTy, val, val);
- break;
- case TGSI_SAT_MINUS_PLUS_ONE:
- mkOp2(OP_MAX, dstTy, val, val, mkImm(-1.0f));
- mkOp2(OP_MIN, dstTy, val, val, mkImm(+1.0f));
- break;
- default:
- assert(!"invalid saturation mode");
- break;
}
Value *ptr = NULL;
dst = tgsi_dst(fpc, &finst->Dst[0]);
mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
- sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
+ sat = finst->Instruction.Saturate;
switch (finst->Instruction.Opcode) {
case TGSI_OPCODE_ABS:
final_dst = dst = tgsi_dst(vpc, &finst->Dst[0]);
mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
- if(finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE) {
+ if(finst->Instruction.Saturate) {
assert(finst->Instruction.Opcode != TGSI_OPCODE_ARL);
if (vpc->is_nv4x)
sat = TRUE;
return FALSE;
}
- if(finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE && !vpc->is_nv4x) {
+ if(finst->Instruction.Saturate && !vpc->is_nv4x) {
if (!vpc->r_0_1.type)
vpc->r_0_1 = constant(vpc, -1, 0, 1, 0, 0);
nvfx_vp_emit(vpc, arith(0, VEC, MAX, dst, mask, nvfx_src(dst), swz(nvfx_src(vpc->r_0_1), X, X, X, X), none));
static unsigned translate_saturate(unsigned saturate)
{
- switch(saturate) {
- default:
- fprintf(stderr, "Unknown saturate mode: %i\n", saturate);
- /* fall-through */
- case TGSI_SAT_NONE: return RC_SATURATE_NONE;
- case TGSI_SAT_ZERO_ONE: return RC_SATURATE_ZERO_ONE;
- }
+ return saturate ? RC_SATURATE_ZERO_ONE : RC_SATURATE_NONE;
}
static unsigned translate_register_file(unsigned file)
}
}
+static LLVMValueRef radeon_llvm_saturate(struct lp_build_tgsi_context *bld_base,
+ LLVMValueRef value)
+{
+ struct lp_build_emit_data clamp_emit_data;
+
+ memset(&clamp_emit_data, 0, sizeof(clamp_emit_data));
+ clamp_emit_data.arg_count = 3;
+ clamp_emit_data.args[0] = value;
+ clamp_emit_data.args[2] = bld_base->base.one;
+ clamp_emit_data.args[1] = bld_base->base.zero;
+
+ return lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP,
+ &clamp_emit_data);
+}
+
static void
emit_store(
struct lp_build_tgsi_context * bld_base,
struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
- struct lp_build_context base = bld->bld_base.base;
const struct tgsi_full_dst_register *reg = &inst->Dst[0];
LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder;
LLVMValueRef temp_ptr;
TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
LLVMValueRef value = dst[chan_index];
- if (inst->Instruction.Saturate != TGSI_SAT_NONE) {
- struct lp_build_emit_data clamp_emit_data;
-
- memset(&clamp_emit_data, 0, sizeof(clamp_emit_data));
- clamp_emit_data.arg_count = 3;
- clamp_emit_data.args[0] = value;
- clamp_emit_data.args[2] = base.one;
-
- switch(inst->Instruction.Saturate) {
- case TGSI_SAT_ZERO_ONE:
- clamp_emit_data.args[1] = base.zero;
- break;
- case TGSI_SAT_MINUS_PLUS_ONE:
- clamp_emit_data.args[1] = LLVMConstReal(
- base.elem_type, -1.0f);
- break;
- default:
- assert(0);
- }
- value = lp_build_emit_llvm(bld_base, TGSI_OPCODE_CLAMP,
- &clamp_emit_data);
- }
+ if (inst->Instruction.Saturate)
+ value = radeon_llvm_saturate(bld_base, value);
if (reg->Register.File == TGSI_FILE_ADDRESS) {
temp_ptr = bld->addr[reg->Register.Index][chan_index];
emit->key.fkey.tex[unit].swizzle_b != PIPE_SWIZZLE_BLUE ||
emit->key.fkey.tex[unit].swizzle_a != PIPE_SWIZZLE_ALPHA);
- boolean saturate = insn->Instruction.Saturate != TGSI_SAT_NONE;
+ boolean saturate = insn->Instruction.Saturate;
/* If doing compare processing or tex swizzle or saturation, we need to put
* the fetched color into a temporary so it can be used as a source later on.
#define TGSI_OPCODE_DSSG 222
#define TGSI_OPCODE_LAST 223
-#define TGSI_SAT_NONE 0 /* do not saturate */
-#define TGSI_SAT_ZERO_ONE 1 /* clamp to [0,1] */
-#define TGSI_SAT_MINUS_PLUS_ONE 2 /* clamp to [-1,1] */
-
/**
* Opcode is the operation code to execute. A given operation defines the
* semantics how the source registers (if any) are interpreted and what is
unsigned Type : 4; /* TGSI_TOKEN_TYPE_INSTRUCTION */
unsigned NrTokens : 8; /* UINT */
unsigned Opcode : 8; /* TGSI_OPCODE_ */
- unsigned Saturate : 2; /* TGSI_SAT_ */
+ unsigned Saturate : 1; /* BOOL */
unsigned NumDstRegs : 2; /* UINT */
unsigned NumSrcRegs : 4; /* UINT */
unsigned Predicate : 1; /* BOOL */
unsigned Label : 1;
unsigned Texture : 1;
- unsigned Padding : 1;
+ unsigned Padding : 2;
};
/*