r600: Typos and whitespace fixes

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c
index 20945ece155fae3fde597d509246975cce74d62a..74250ae81392f48794f7b8ae662a478aba2a1f4a 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -723,7 +723,7 @@ static void evergreen_set_global_binding(
  * command stream by the start_cs_cmd atom.  However, since the SET_CONTEXT_REG
  * packet requires that the shader type bit be set, we must initialize all
  * context registers needed for compute in this function.  The registers
- * intialized by the start_cs_cmd atom can be found in evereen_state.c in the
+ * initialized by the start_cs_cmd atom can be found in evergreen_state.c in the
  * functions evergreen_init_atom_start_cs or cayman_init_atom_start_cs depending
  * on the GPU family.
  */
@@ -733,7 +733,7 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx)
        int num_threads;
        int num_stack_entries;
 
-       /* since all required registers are initialised in the
+       /* since all required registers are initialized in the
         * start_compute_cs_cmd atom, we can EMIT_EARLY here.
         */
        r600_init_command_buffer(cb, 256);
@@ -818,7 +818,7 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx)
                 * R_008E28_SQ_STATIC_THREAD_MGMT3
                 */
 
-               /* XXX: We may need to adjust the thread and stack resouce
+               /* XXX: We may need to adjust the thread and stack resource
                 * values for 3D/compute interop */
 
                r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 9dfb84965cf980d7ab7c08eaaa1f0904bedbe4bb..f4e10cf070227ef7eb899a2803acb94bdfb3d195 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3670,9 +3670,9 @@ void evergreen_init_state_functions(struct r600_context *rctx)
        unsigned id = 1;
        unsigned i;
        /* !!!
-        *  To avoid GPU lockup registers must be emited in a specific order
+        *  To avoid GPU lockup registers must be emitted in a specific order
         * (no kidding ...). The order below is important and have been
-        * partialy infered from analyzing fglrx command stream.
+        * partially inferred from analyzing fglrx command stream.
         *
         * Don't reorder atom without carefully checking the effect (GPU lockup
         * or piglit regression).

diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index 0b78290295a343b46b6126b2a7436e3320988a66..1629399d8fece398f07a4732824828d9ce3f371a 100644 (file)
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -245,8 +245,8 @@ struct r600_bytecode {
        unsigned        ar_chan;
        unsigned        ar_handling;
        unsigned        r6xx_nop_after_rel_dst;
-       bool            index_loaded[2];
-       unsigned        index_reg[2]; /* indexing register CF_INDEX_[01] */
+       bool            index_loaded[2];
+       unsigned        index_reg[2]; /* indexing register CF_INDEX_[01] */
        unsigned        debug_id;
        struct r600_isa* isa;
 };