(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 677651f86db79ffcec8423001fcdd8ff95fb8a98..de6a2eaa0a814e61e9625e46707a9ed8b655e9f3 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -596,7 +596,7 @@ What the designers did however was not to add new Load-Store
 or Arithmetic instructions to RISC-V, but instead to "mark"
 registers with a tag.  These tags tell the CPU: when you are asked to
 carry out
-an add instruction on r6 and r7, do not take r6 or r7 from the reguster
+an add instruction on r6 and r7, do not take r6 or r7 from the register
 file, instead please perform a Cache-coherent Load-with-Increment
 on each, using special Address Registers for each.  Each new use
 of r6 therefore brings in an entirely new value *directly from