fix gram unit test imports

diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py
index 2a96b3d872b423fbebf3f23f68e366f7d87d14a2..ceb8f664d01fa349e8b83c62cc95ddb07ef28dc2 100644 (file)
--- a/gram/test/test_soc.py
+++ b/gram/test/test_soc.py
@@ -1,6 +1,7 @@
 # This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
 
 import random
+import unittest
 
 from nmigen import *
 from nmigen.asserts import Assert, Assume
@@ -19,6 +20,7 @@ from gram.frontend.wishbone import gramWishbone
 from gram.core.multiplexer import _AntiStarvation
 from gram.test.utils import *
 
+
 class DDR3SoC(SoC, Elaboratable):
     def __init__(self, *, clk_freq, dramcore_addr,
                  ddr_addr):
@@ -221,3 +223,7 @@ class SocTestCase(FHDLTestCase):
                 self.assertEqual(0xFACE0000 | i, (yield from wb_read(soc.bus, (0x10000000 >> 2) + i, 0xF, 256)))
 
         runSimulation(soc, process, "test_soc_continuous_memtest.vcd")
+
+
+if __name__ == '__main__':
+    unittest.main()

diff --git a/gram/test/utils.py b/gram/test/utils.py
index ed34d11000e2f0056e3625f1b47961d4523c7ac7..73fb96e44e31672de6679b53ad61d3568093c6b1 100644 (file)
--- a/gram/test/utils.py
+++ b/gram/test/utils.py
@@ -9,7 +9,7 @@ import warnings
 from contextlib import contextmanager
 
 from nmigen import *
-from nmigen.sim.pysim import *
+from nmigen.sim import *
 from nmigen.hdl.ir import Fragment
 from nmigen.back import rtlil
 from nmigen._toolchain import require_tool