altivec.md: (andvv16qi3...
authorOlga Golovanevsky <olga@il.ibm.com>
Sun, 28 Mar 2004 15:07:21 +0000 (15:07 +0000)
committerDorit Nuzman <dorit@gcc.gnu.org>
Sun, 28 Mar 2004 15:07:21 +0000 (15:07 +0000)
* config/rs6000/altivec.md: (andvv16qi3, andv8hi3, one_cmplv16qi2,
        one_cmplv8hi2, one_cmplv4si2, iorv16qi3, iorv8hi3,): New modelling.

Co-Authored-By: Dorit Naishlos <dorit@il.ibm.com>
From-SVN: r80039

gcc/ChangeLog
gcc/config/rs6000/altivec.md

index 281ab227e3bfabb2ec1a0d7959d62dc288e9bd84..bb64ccc6b22a45491cad82cc934e8269ee5881d0 100644 (file)
@@ -1,3 +1,9 @@
+2004-03-28  Olga Golovonevsky <olga@il.ibm.com>
+            Dorit Naishlos <dorit@il.ibm.com>
+
+        * config/rs6000/altivec.md: (andvv16qi3, andv8hi3, one_cmplv16qi2,
+        one_cmplv8hi2, one_cmplv4si2, iorv16qi3, iorv8hi3,): New modelling.
+
 2004-03-28  Stephane Carrez  <stcarrez@nerim.fr>
 
        * config/m68hc11/m68hc11-protos.h (m68hc11_page0_symbol_p): Declare.
index 2ede79d9f5c8c5cae44631d803d30c290a42253c..684a5d4c4b97cf24dda742aeda3fa65085b61973 100644 (file)
   "vaddsws %0,%1,%2"
   [(set_attr "type" "vecsimple")])
 
+(define_insn "andv16qi3"
+  [(set (match_operand:V16QI 0 "register_operand" "=v")
+        (and:V16QI (match_operand:V16QI 1 "register_operand" "v")
+                  (match_operand:V16QI 2 "register_operand" "v")))]
+  "TARGET_ALTIVEC"
+  "vand %0,%1,%2"
+  [(set_attr "type" "vecsimple")])
+
+(define_insn "andv8hi3"
+  [(set (match_operand:V8HI 0 "register_operand" "=v")
+        (and:V8HI (match_operand:V8HI 1 "register_operand" "v")
+                  (match_operand:V8HI 2 "register_operand" "v")))]
+  "TARGET_ALTIVEC"
+  "vand %0,%1,%2"
+  [(set_attr "type" "vecsimple")])
+
 (define_insn "andv4si3"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (and:V4SI (match_operand:V4SI 1 "register_operand" "v")
   "TARGET_ALTIVEC"
   "vnor %0,%1,%2"
   [(set_attr "type" "vecsimple")])
+  
+(define_insn "one_cmplv16qi2"
+  [(set (match_operand:V16QI 0 "register_operand" "=v")
+        (not:V16QI (match_operand:V16QI 1 "register_operand" "v")))]
+  "TARGET_ALTIVEC"
+  "vnot %0,%1"
+  [(set_attr "type" "vecsimple")])
+  
+(define_insn "one_cmplv8hi2"
+  [(set (match_operand:V8HI 0 "register_operand" "=v")
+        (not:V8HI (match_operand:V8HI 1 "register_operand" "v")))]
+  "TARGET_ALTIVEC"
+  "vnot %0,%1"
+  [(set_attr "type" "vecsimple")])
+  
+(define_insn "one_cmplv4si2"
+  [(set (match_operand:V4SI 0 "register_operand" "=v")
+        (not:V4SI (match_operand:V4SI 1 "register_operand" "v")))]
+  "TARGET_ALTIVEC"
+  "vnot %0,%1"
+  [(set_attr "type" "vecsimple")])
+
+(define_insn "iorv16qi3"
+  [(set (match_operand:V16QI 0 "register_operand" "=v")
+        (ior:V16QI (match_operand:V16QI 1 "register_operand" "v")
+                  (match_operand:V16QI 2 "register_operand" "v")))]
+  "TARGET_ALTIVEC"
+  "vor %0,%1,%2"
+  [(set_attr "type" "vecsimple")])
+
+(define_insn "iorv8hi3"
+  [(set (match_operand:V8HI 0 "register_operand" "=v")
+        (ior:V8HI (match_operand:V8HI 1 "register_operand" "v")
+                  (match_operand:V8HI 2 "register_operand" "v")))]
+  "TARGET_ALTIVEC"
+  "vor %0,%1,%2"
+  [(set_attr "type" "vecsimple")])
 
 (define_insn "iorv4si3"
   [(set (match_operand:V4SI 0 "register_operand" "=v")