how many registers are to be considered Indices.
With these Hazard Mitigations in place, high-performance implementations
-may read-cache the Indices from the point where a given `svindex` instruction
-is called (or SVSHAPE SPRs - and MAXVL- directly altered).
+may read-cache the Indices at the point where a given `svindex` instruction
+is called (or SVSHAPE SPRs - and MAXVL - directly altered) by issuing
+background GPR register file reads whilst other instructions are being
+issued and executed.
The original motivation for Indexed REMAP was to mitigate the need to add
an expensive `mv.x` to the Scalar ISA, which was likely to be rejected as