+2018-11-21 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/87839
+ * config/aarch64/atomics.md (@aarch64_compare_and_swap<mode>): Use
+ rIJ constraint for aarch64_plus_operand rather than rn.
+
2018-11-21 Renlin Li <renlin.li@arm.com>
PR middle-end/84877
(match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
(set (match_dup 1)
(unspec_volatile:GPI
- [(match_operand:GPI 2 "aarch64_plus_operand" "rn") ;; expect
+ [(match_operand:GPI 2 "aarch64_plus_operand" "rIJ") ;; expect
(match_operand:GPI 3 "aarch64_reg_or_zero" "rZ") ;; desired
(match_operand:SI 4 "const_int_operand") ;; is_weak
(match_operand:SI 5 "const_int_operand") ;; mod_s
--- /dev/null
+/* PR target/87839 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -w" } */
+
+long long b[64];
+void foo (void);
+int bar (void (*) (void));
+void qux (long long *, long long) __attribute__((noreturn));
+void quux (long long *, long long);
+
+void
+baz (void)
+{
+ __sync_val_compare_and_swap (b, 4294967298LL, 78187493520LL);
+ __sync_bool_compare_and_swap (b + 1, 8589934595LL, 21474836489LL);
+ __sync_fetch_and_xor (b, 60129542145LL);
+ quux (b, 42949672967LL);
+ __sync_xor_and_fetch (b + 22, 60129542145LL);
+ quux (b + 23, 42949672967LL);
+ if (bar (baz))
+ __builtin_abort ();
+ foo ();
+ __sync_val_compare_and_swap (b, 4294967298LL, 0);
+ __sync_bool_compare_and_swap (b + 1, 8589934595LL, 78187493520LL);
+ if (__sync_or_and_fetch (b, 21474836489LL) != 21474836489LL)
+ qux (b + 22, 60129542145LL);
+ __atomic_fetch_nand (b + 23, 42949672967LL, __ATOMIC_RELAXED);
+ bar (baz);
+}