radeonsi: set correct alignment for texture buffers and constant buffers

I think these are all equivalent to vertex buffer fetches which should be
dword-aligned. Scalar loads are also dword-aligned.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 0efd4ebcb85526feab21da1764e1c4b8848c51cc..08502698d39ecad2046d1cff1404670babb6955f 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -265,13 +265,12 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                 return 64;
 
        case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
-               return 256;
+       case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
+               return 4;
 
        case PIPE_CAP_GLSL_FEATURE_LEVEL:
                return HAVE_LLVM >= 0x0305 ? 330 : 140;
 
-       case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
-               return 1;
        case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
                return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);