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Make consistent
author
Eddie Hung
<eddie@fpgeh.com>
Thu, 18 Jul 2019 22:21:23 +0000
(15:21 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Thu, 18 Jul 2019 22:21:23 +0000
(15:21 -0700)
techlibs/common/mul2dsp.v
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diff --git
a/techlibs/common/mul2dsp.v
b/techlibs/common/mul2dsp.v
index 2819c939e1bb909425a7a6c438fde0e1c00c7304..ee53701eea9c61cd8b985e29b8548e8e3eaaee78 100644
(file)
--- a/
techlibs/common/mul2dsp.v
+++ b/
techlibs/common/mul2dsp.v
@@
-201,7
+201,8
@@
module \$__mul_gen (A, B, Y);
.B(B[B_WIDTH-1 : (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)]),
\r
.Y(partial[n-1])
\r
);
\r
- assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
\r
+ assign partial_sum[n-1] = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2];
\r
+ assign Y = partial_sum[n-1];
\r
end
\r
else begin
\r
if (A_SIGNED)
\r