back.pysim: make initial phase configurable.

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index f0bfba101370af2b1723eaa8c778e9daf58a729f..d09c981793f1da385c3bbfa10539e2b4205e98c6 100644 (file)
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -250,15 +250,17 @@ class Simulator:
                 pass
         self.add_process(sync_process())
 
-    def add_clock(self, period, domain="sync"):
+    def add_clock(self, period, phase=None, domain="sync"):
         if self._fastest_clock == self._epsilon or period < self._fastest_clock:
             self._fastest_clock = period
 
         half_period = period / 2
+        if phase is None:
+            phase = half_period
         clk = self._domains[domain].clk
         def clk_process():
             yield Passive()
-            yield Delay(half_period)
+            yield Delay(phase)
             while True:
                 yield clk.eq(1)
                 yield Delay(half_period)

diff --git a/nmigen/compat/sim/__init__.py b/nmigen/compat/sim/__init__.py
index 4ee04549442d2cb60d5dd1bfe07a97a816ee282f..8219cf9d90b09358808966526532a3faa1aa9840 100644 (file)
--- a/nmigen/compat/sim/__init__.py
+++ b/nmigen/compat/sim/__init__.py
@@ -18,7 +18,7 @@ def run_simulation(fragment_or_module, generators, clocks={"sync": 10}, vcd_name
 
     with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim:
         for domain, period in clocks.items():
-            sim.add_clock(period / 1e9, domain)
+            sim.add_clock(period / 1e9, domain=domain)
         for domain, process in generators.items():
-            sim.add_sync_process(process, domain)
+            sim.add_sync_process(process, domain=domain)
         sim.run()