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diff --git a/nlnet_2023_simplev_riscv.mdwn b/nlnet_2023_simplev_riscv.mdwn
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@@ -28,9 +28,9 @@ if you need any HTML to make your point please include this as attachment.
 
 ## Abstract: Can you explain the whole project and its expected outcome(s).
 
-This project, a collaboration between RED Semiconductor and LibreSOC, will build on work already completed in bringing Simple-V/SVP64 ISA-agnostic vectorised microprocessor architecture to the RISC-V community, creating an open-source ISA who's performance matches with high-end incumbents like ARM, Intel and IBM. Bringing open-source High Performance Computing to all developers, will fuel the next wave of innovation. The outcome of the project will be the validation of Simple-V/SVP64 architecture on RISC-V base architecture, demonstrated in a software simulator.
+This project, a collaboration between RED Semiconductor and LibreSOC, will build on work already completed in bringing Simple-V  ISA-agnostic vectorised microprocessor architecture to the RISC-V community, creating an open-source ISA who's performance matches with high-end incumbents like ARM, Intel and IBM. Bringing open-source High Performance Computing to all developers, will fuel the next wave of innovation. The outcome of the project will be the validation of Simple-V architecture on RISC-V base architecture, demonstrated in a software simulator.
 
-RISC-V is the largest open-source global community for microprocessor architecture enabling developers to create custom instructions to solve computational challenges, and develop their own SoC hardware implementations. Simple-V/SVP64 extensions will deliver accelerated  CPU performance for rapidly growing demands at the Edge for data processing, autonomy and cryptography, driven by global megatrends like AI, metaverse and social media, as well as social issues like healthcare and critical infrastructure. This project enables the developer community to access the benefits of Simple-V/SVP64 code efficiency on RISC-V.
+RISC-V is the largest open-source global community for microprocessor architecture enabling developers to create custom instructions to solve computational challenges, and develop their own SoC hardware implementations. Simple-V extensions will deliver accelerated  CPU performance for rapidly growing demands at the Edge for data processing, autonomy and cryptography, driven by global megatrends like AI, metaverse and social media, as well as social issues like healthcare and critical infrastructure. This project enables the developer community to access the benefits of Simple-V code efficiency on RISC-V.
 
 
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
@@ -51,7 +51,6 @@ EUR 100,000.
 
 # Explain what the requested budget will be used for? 
 
-
 Key phases of this project are:
 
 * Assessment of the missing RISC-V instructions (RISC-V RV64GC is only 96 instructions