alpha.md (one_cmpl<mode>2, [...]): New macroized vector operate patterns.

        * config/alpha/alpha.md (one_cmpl<mode>2, and<mode>3, andnot<mode>3,
        ior<mode>3, iornot<mode>3, xor<mode>3, xornot<mode>3): New macroized
        vector operate patterns.

From-SVN: r92545

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1fa3c957c0496e4883b8a5a795e610f4bec9dc4b..3ddbf232ac63a593f8c62509edd441123b32ed02 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2004-12-23  Richard Henderson  <rth@redhat.com>
+
+       * config/alpha/alpha.md (one_cmpl<mode>2, and<mode>3, andnot<mode>3,
+       ior<mode>3, iornot<mode>3, xor<mode>3, xornot<mode>3): New macroized
+       vector operate patterns.
+
 2004-12-23  Richard Henderson  <rth@redhat.com>
 
        * config/i386/i386.c (ix86_expand_vector_move): Tidy.

diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 145e23c48a58611d9be63c9fbeff93f1d88a5dfd..2679324d10a5f63c21598f6f13c2ecec32e1c6b3 100644 (file)
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -6207,6 +6207,61 @@
   "TARGET_MAX"
   "maxsw4 %r1,%r2,%0"
   [(set_attr "type" "mvi")])
+
+(define_insn "one_cmpl<mode>2"
+  [(set (match_operand:VEC 0 "register_operand" "=r")
+       (not:VEC (match_operand:VEC 1 "register_operand" "r")))]
+  ""
+  "ornot $31,%1,%0"
+  [(set_attr "type" "ilog")])
+
+(define_insn "and<mode>3"
+  [(set (match_operand:VEC 0 "register_operand" "=r")
+       (and:VEC (match_operand:VEC 1 "register_operand" "r")
+                (match_operand:VEC 2 "register_operand" "r")))]
+  ""
+  "and %1,%2,%0"
+  [(set_attr "type" "ilog")])
+
+(define_insn "*andnot<mode>3"
+  [(set (match_operand:VEC 0 "register_operand" "=r")
+       (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r"))
+                (match_operand:VEC 2 "register_operand" "r")))]
+  ""
+  "bic %2,%1,%0"
+  [(set_attr "type" "ilog")])
+
+(define_insn "ior<mode>3"
+  [(set (match_operand:VEC 0 "register_operand" "=r")
+       (ior:VEC (match_operand:VEC 1 "register_operand" "r")
+                (match_operand:VEC 2 "register_operand" "r")))]
+  ""
+  "bis %1,%2,%0"
+  [(set_attr "type" "ilog")])
+
+(define_insn "*iornot<mode>3"
+  [(set (match_operand:VEC 0 "register_operand" "=r")
+       (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r"))
+                (match_operand:VEC 2 "register_operand" "r")))]
+  ""
+  "ornot %2,%1,%0"
+  [(set_attr "type" "ilog")])
+
+(define_insn "xor<mode>3"
+  [(set (match_operand:VEC 0 "register_operand" "=r")
+       (xor:VEC (match_operand:VEC 1 "register_operand" "r")
+                (match_operand:VEC 2 "register_operand" "r")))]
+  ""
+  "xor %1,%2,%0"
+  [(set_attr "type" "ilog")])
+
+(define_insn "*xornot<mode>3"
+  [(set (match_operand:VEC 0 "register_operand" "=r")
+       (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r")
+                         (match_operand:VEC 2 "register_operand" "r"))))]
+  ""
+  "eqv %1,%2,%0"
+  [(set_attr "type" "ilog")])
 \f
 ;; Bit field extract patterns which use ext[wlq][lh]