+2002-11-12 Kazu Hirata <kazu@cs.umass.edu>
+
+ * config/h8300/h8300.c (single_one_operand): Correctly compute
+ mask when mode is SImode.
+ (single_zero_operand): Likewise.
+ * config/h8300/h8300.md (two new anonymous insns): New.
+
2002-11-12 Gerald Pfeifer <pfeifer@dbai.tuwien.ac.at>
* doc/contrib.texi (Contributors): Use GCJ instead of gcj to refer
/* We really need to do this masking because 0x80 in QImode is
represented as -128 for example. */
unsigned HOST_WIDE_INT mask =
- ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1;
+ (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
+ ? ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1
+ : ~0;
unsigned HOST_WIDE_INT value = INTVAL (operand);
if (exact_log2 (value & mask) >= 0)
/* We really need to do this masking because 0x80 in QImode is
represented as -128 for example. */
unsigned HOST_WIDE_INT mask =
- ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1;
+ (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
+ ? ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1
+ : ~0;
unsigned HOST_WIDE_INT value = INTVAL (operand);
if (exact_log2 (~value & mask) >= 0)
[(set_attr "length" "2")
(set_attr "cc" "set_zn")])
+(define_insn ""
+ [(set (cc0)
+ (and:HI (match_operand:HI 0 "register_operand" "r")
+ (match_operand:HI 1 "single_one_operand" "n")))]
+ ""
+ "*
+{
+ operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
+ if (INTVAL (operands[1]) > 128)
+ {
+ operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
+ return \"btst\\t%V1,%t0\";
+ }
+ return \"btst\\t%V1,%s0\";
+}"
+ [(set_attr "length" "2")
+ (set_attr "cc" "set_zn")])
+
+(define_insn ""
+ [(set (cc0)
+ (and:SI (match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "single_one_operand" "n")))]
+ "(TARGET_H8300H || TARGET_H8300S)
+ && (INTVAL (operands[1]) & 0xffff) != 0"
+ "*
+{
+ operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
+ if (INTVAL (operands[1]) > 128)
+ {
+ operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
+ return \"btst\\t%V1,%x0\";
+ }
+ return \"btst\\t%V1,%w0\";
+}"
+ [(set_attr "length" "2")
+ (set_attr "cc" "set_zn")])
+
(define_insn "tstqi"
[(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
""