hdl.ast: cast Mux() selector to bool if it is not a 1-bit value.

Fixes #232.

diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py
index d7ae0924cea246df028d7106d52612629c46b1ed..2dee3ffcd937962c2b0cd887b7bc303d887a9798 100644 (file)
--- a/nmigen/hdl/ast.py
+++ b/nmigen/hdl/ast.py
@@ -523,6 +523,8 @@ def Mux(sel, val1, val0):
     Value, out
         Output ``Value``. If ``sel`` is asserted, the Mux returns ``val1``, else ``val0``.
     """
+    if len(sel) != 1:
+        sel = Value.wrap(sel).bool()
     return Operator("m", [sel, val1, val0])
 
 

diff --git a/nmigen/test/test_hdl_ast.py b/nmigen/test/test_hdl_ast.py
index 1029c822276b0ace6a2c03f3263fe2f1d0e394d5..143de35de4176ee6ca6344c7ab829e0ee77cb8f6 100644 (file)
--- a/nmigen/test/test_hdl_ast.py
+++ b/nmigen/test/test_hdl_ast.py
@@ -276,6 +276,11 @@ class OperatorTestCase(FHDLTestCase):
         v4 = Mux(s, Const(0, (4, False)), Const(0, (4, True)))
         self.assertEqual(v4.shape(), (5, True))
 
+    def test_mux_wide(self):
+        s = Const(0b100)
+        v = Mux(s, Const(0, (4, False)), Const(0, (6, False)))
+        self.assertEqual(repr(v), "(m (b (const 3'd4)) (const 4'd0) (const 6'd0))")
+
     def test_bool(self):
         v = Const(0).bool()
         self.assertEqual(repr(v), "(b (const 1'd0))")