o3cpu build for mips

--HG--
extra : convert_revision : 2c0be7a8c0a54ba5b1b2b69468f788d20abc8452

diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index c8e85a7543448411584f3b61dbd793213b6df605..81e2318100b84235c39379499e509bcfce63e6d9 100644 (file)
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -117,7 +117,7 @@ output exec {{
     /** return data in cases where there the size of data is only
         known in the packet
     */
-    uint64_t getStoreData(Packet *packet) {
+    uint64_t getStoreData(%(CPU_exec_context)s *xc, Packet *packet) {
         switch (packet->getSize())
         {
           case 8:
@@ -542,7 +542,7 @@ def template StoreCompleteAcc {{
         if (fault == NoFault) {
             %(op_wb)s;
 
-            if (traceData) { traceData->setData(getStoreData(pkt)); }
+            if (traceData) { traceData->setData(getStoreData(xc, pkt)); }
         }
 
         return fault;

diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh
index cf78c0941b7b9e1587eac55497097bf5c1e945ae..7cd53413bbcf1cdbeac9e4785e06080d1bd25953 100755 (executable)
--- a/src/cpu/o3/mips/dyn_inst.hh
+++ b/src/cpu/o3/mips/dyn_inst.hh
@@ -107,7 +107,7 @@ class MipsDynInst : public BaseDynInst<Impl>
     /** Reads a misc. register, including any side-effects the read
      * might have as defined by the architecture.
      */
-    MiscReg readMiscReg(int misc_reg)
+    MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
     {
         return this->cpu->readMiscReg(misc_reg, this->threadNumber);
     }
@@ -122,12 +122,13 @@ class MipsDynInst : public BaseDynInst<Impl>
     /** Sets a misc. register, including any side-effects the write
      * might have as defined by the architecture.
      */
-    void setMiscReg(int misc_reg, const MiscReg &val)
+    void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
     {
         return this->cpu->setMiscReg(misc_reg, val,
                                                this->threadNumber);
     }
 
+
     /** Calls a syscall. */
     void syscall(int64_t callnum);
 
@@ -206,6 +207,55 @@ class MipsDynInst : public BaseDynInst<Impl>
         BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
     }
 
+    /** Reads a miscellaneous register. */
+    TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
+    {
+        return this->cpu->readMiscRegNoEffect(
+                si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
+                this->threadNumber);
+    }
+
+    /** Reads a misc. register, including any side-effects the read
+     * might have as defined by the architecture.
+     */
+    TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
+    {
+        return this->cpu->readMiscReg(
+                si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
+                this->threadNumber);
+    }
+
+    /** Sets a misc. register. */
+    void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
+    {
+        this->instResult.integer = val;
+        return this->cpu->setMiscRegNoEffect(
+                si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
+                val, this->threadNumber);
+    }
+
+    /** Sets a misc. register, including any side-effects the write
+     * might have as defined by the architecture.
+     */
+    void setMiscRegOperand(const StaticInst *si, int idx,
+                                     const MiscReg &val)
+    {
+        return this->cpu->setMiscReg(
+                si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
+                val, this->threadNumber);
+    }
+
+    uint64_t readRegOtherThread(int misc_reg)
+    {
+        panic("MIPS MT not defined for O3 CPU.\n");
+        return 0;
+    }
+
+    void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
+    {
+        panic("MIPS MT not defined for O3 CPU.\n");
+    }
+
   public:
     /** Calculates EA part of a memory instruction. Currently unused,
      * though it may be useful in the future if we want to split