(no commit message)

diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index 17c4a99e06f323eca8dba47a5b81160e0e743283..e0eabf38b387ab3f3e3d94a286d4bc7ba9a8f3a5 100644 (file)
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -59,10 +59,12 @@ SVSTATE contains (and permits setting of):
 * UnPack - if set then dststep/dsubstep VL/SUBVL loop-ordering is inverted.
 * hphint - Horizontal Parallelism Hint. Indicates that
   no Hazards exist between groups of elements in sequential multiples of this number
-   (before REMAP).  By definition: elements for which `FLOOR(srcstep/hphint)` is
-   equal *before REMAP* are in the same parallelism "group". In Vertical First Mode
-   hardware **MUST ONLY** process elements in the same group, and must stop
-   Horizontal Issue at the last element of a given group. Set to zero to indicate "no hint".
+   (before REMAP).  By definition: elements for which `FLOOR(step/hphint)` is
+   equal *before REMAP* are in the same parallelism "group", for both
+   `srcstep` and `dststep`. In Vertical First Mode
+   hardware **MUST** respect Strict Program Order but is permitted to
+   merge multiple scalar loops into parallel batches, if Reservation Station resources
+   are sufficient.  Set to zero to indicate "no hint".
 * SVme - REMAP enable bits, indicating which register is to be
    REMAPed: RA, RB, RC, RT and EA are the canonical (typical) register names
    associated with each bit, with RA being the LSB and EA being the MSB.