ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 45233a7646c0c24808f184500c0d0cab6a26ee82..d100efb8ee7705ebc7a98bb1f1dcebd3f4c022e6 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -93,6 +93,10 @@ namespace ArmISA
         Bitfield<4, 0> mode;
     EndBitUnion(CPSR)
 
+    // This mask selects bits of the CPSR that actually go in the CondCodes
+    // integer register to allow renaming.
+    static const uint32_t CondCodesMask = 0xF80F0000;
+
     BitUnion32(SCTLR)
         Bitfield<30> te;  // Thumb Exception Enable
         Bitfield<29> afe; // Access flag enable