Replace Memory with MemObject; no need for two different levels of hierarchy there.

Get rid of addPort().
Change getPort() behavior on PhysicalMemory.

SConscript:
cpu/simple/cpu.hh:
sim/system.cc:
sim/system.hh:
    Replace Memory with MemObject.
cpu/base.hh:
    No need to declare Port here anymore.
cpu/cpu_exec_context.hh:
    Need PageTable definition.
cpu/simple/cpu.cc:
mem/physical.cc:
mem/physical.hh:
    Replace Memory with MemObject.
    Get rid of addPort(); allow getting anonymous ports with getPort().
mem/translating_port.hh:
    Remove unneeded header.
sim/process.cc:
    Replace Memory with MemObject.
    Change how initialization port gets set up to deal with change in
    addPort()/getPort().  Current solution is not ideal but it works.
sim/process.hh:
    Remove unneeded headers and declarations.
    Make LiveProcess::getDesc() abstract instead of panicing if called.
sim/syscall_emul.hh:
    Fix includes.

--HG--
extra : convert_revision : 11d4ffb54230038afcf7219cc46e51f809329a2f

diff --git a/SConscript b/SConscript
index ae7602c9dbd991887b9057fb8b87fd26f8bdf21d..e9957e143e551f38679341b08fdf8e9f16357621 100644 (file)
--- a/SConscript
+++ b/SConscript
@@ -88,7 +88,7 @@ base_sources = Split('''
        cpu/static_inst.cc
         cpu/sampler/sampler.cc
 
-        mem/memory.cc
+        mem/mem_object.cc
         mem/page_table.cc
         mem/physical.cc
         mem/port.cc

diff --git a/cpu/base.hh b/cpu/base.hh
index 0866b49a7db82523839f939cb51400063bf58d4d..79700c117fa2c49d5810efc31281fe5c9281d0dd 100644 (file)
--- a/cpu/base.hh
+++ b/cpu/base.hh
@@ -42,7 +42,6 @@ class System;
 namespace Kernel { class Statistics; }
 class BranchPred;
 class ExecContext;
-class Port;
 
 class BaseCPU : public SimObject
 {

diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index 509583d6528ea5e2129ab45fd8aece41183a67dc..9268f6f3d45bcbddd542cc68c0df81ff2213a5c9 100644 (file)
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -53,6 +53,7 @@ class MemoryController;
 #else // !FULL_SYSTEM
 
 #include "sim/process.hh"
+#include "mem/page_table.hh"
 class TranslatingPort;
 
 #endif // FULL_SYSTEM

diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 6e87647097f9d8cc7ce19561b70630d31eac456a..b99ace5985212e46231a931c021e3cb8faf0ee67 100644 (file)
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -71,7 +71,7 @@
 #include "arch/stacktrace.hh"
 #include "arch/vtophys.hh"
 #else // !FULL_SYSTEM
-#include "mem/memory.hh"
+#include "mem/mem_object.hh"
 #endif // FULL_SYSTEM
 
 using namespace std;
@@ -152,13 +152,13 @@ SimpleCPU::SimpleCPU(Params *p)
     _status = Idle;
 
     //Create Memory Ports (conect them up)
-    p->mem->addPort("DCACHE");
-    dcachePort.setPeer(p->mem->getPort("DCACHE"));
-    (p->mem->getPort("DCACHE"))->setPeer(&dcachePort);
+    Port *mem_dport = p->mem->getPort();
+    dcachePort.setPeer(mem_dport);
+    mem_dport->setPeer(&dcachePort);
 
-    p->mem->addPort("ICACHE");
-    icachePort.setPeer(p->mem->getPort("ICACHE"));
-    (p->mem->getPort("ICACHE"))->setPeer(&icachePort);
+    Port *mem_iport = p->mem->getPort();
+    icachePort.setPeer(mem_iport);
+    mem_iport->setPeer(&icachePort);
 
 #if FULL_SYSTEM
     cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
@@ -1128,7 +1128,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
     Param<int> cpu_id;
     Param<Tick> profile;
 #else
-    SimObjectParam<Memory *> mem;
+    SimObjectParam<MemObject *> mem;
     SimObjectParam<Process *> workload;
 #endif // FULL_SYSTEM
 

diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 21944a49fcb706a9531ebcdc594076e17afe5723..ed464c605998665239f3ec4eaffe9fe2b28433fa 100644 (file)
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -46,7 +46,7 @@
 class Processor;
 class AlphaITB;
 class AlphaDTB;
-class Memory;
+class MemObject;
 
 class RemoteGDB;
 class GDBListener;
@@ -58,7 +58,6 @@ class Process;
 #endif // FULL_SYSTEM
 
 class ExecContext;
-class MemInterface;
 class Checkpoint;
 
 namespace Trace {
@@ -180,7 +179,7 @@ class SimpleCPU : public BaseCPU
         AlphaITB *itb;
         AlphaDTB *dtb;
 #else
-        Memory *mem;
+        MemObject *mem;
         Process *process;
 #endif
     };

diff --git a/mem/mem_object.cc b/mem/mem_object.cc
new file mode 100644 (file)
index 0000000..f579a07
--- /dev/null
+++ b/mem/mem_object.cc
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/mem_object.hh"
+#include "sim/param.hh"
+
+MemObject::MemObject(const std::string &name)
+    : SimObject(name)
+{
+}
+
+DEFINE_SIM_OBJECT_CLASS_NAME("MemObject", MemObject)

diff --git a/mem/physical.cc b/mem/physical.cc
index a00c5913926b343d056080848f45bfa786257711..c1e83fb9e409f3c1b0cdfb662aff795f16bca840 100644 (file)
--- a/mem/physical.cc
+++ b/mem/physical.cc
@@ -70,7 +70,7 @@ PhysicalMemory::MemResponseEvent::description()
 }
 
 PhysicalMemory::PhysicalMemory(const string &n)
-    : Memory(n), base_addr(0), pmem_addr(NULL)
+    : MemObject(n), base_addr(0), pmem_addr(NULL)
 {
     // Hardcoded to 128 MB for now.
     pmem_size = 1 << 27;
@@ -107,13 +107,6 @@ PhysicalMemory::new_page()
     return return_addr;
 }
 
-Port *
-PhysicalMemory::addPort(std::string portName)
-{
-    memoryPortList[portName] = new MemoryPort(this);
-    return memoryPortList[portName];
-}
-
 int
 PhysicalMemory::deviceBlockSize()
 {
@@ -161,10 +154,11 @@ PhysicalMemory::doFunctionalAccess(Packet &pkt)
 Port *
 PhysicalMemory::getPort(const char *if_name)
 {
-    if (memoryPortList.find(if_name) != memoryPortList.end())
-        return memoryPortList[if_name];
-    else
-        panic("Looking for a port that didn't exist\n");
+    if (if_name == NULL) {
+        return new MemoryPort(this);
+    } else {
+        panic("PhysicalMemory::getPort: unknown port %s requested", if_name);
+    }
 }
 
 void

diff --git a/mem/physical.hh b/mem/physical.hh
index 658ba18ff355bb703d6956348349a087660ef48f..b066d3dfc069b31c7dedace4b950f9f8af3c2571 100644 (file)
--- a/mem/physical.hh
+++ b/mem/physical.hh
@@ -33,16 +33,17 @@
 #define __PHYSICAL_MEMORY_HH__
 
 #include "base/range.hh"
-#include "mem/memory.hh"
+#include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/port.hh"
 #include "sim/eventq.hh"
 #include <map>
 #include <string>
+
 //
 // Functional model for a contiguous block of physical memory. (i.e. RAM)
 //
-class PhysicalMemory : public Memory
+class PhysicalMemory : public MemObject
 {
     class MemoryPort : public Port
     {
@@ -68,12 +69,8 @@ class PhysicalMemory : public Memory
         virtual int deviceBlockSize();
     };
 
-    std::map<std::string, MemoryPort*> memoryPortList;
-
     virtual Port * getPort(const char *if_name);
 
-    virtual Port * addPort(std::string portName);
-
     int numPorts;
 
     int lat;

diff --git a/mem/translating_port.hh b/mem/translating_port.hh
index acbc3fabc21449dfb22724329e112f33e7b028d2..2ba3d68e2eb9418a9bf5ed3e60d8cf7d5cc1482a 100644 (file)
--- a/mem/translating_port.hh
+++ b/mem/translating_port.hh
@@ -29,8 +29,6 @@
 #ifndef __MEM_TRANSLATING_PROT_HH__
 #define __MEM_TRANSLATING_PROT_HH__
 
-#include "mem/memory.hh"
-
 class Port;
 class PageTable;
 

diff --git a/sim/process.cc b/sim/process.cc
index 2eeb872342a8dee83b900a3c1e0f299800fd2a1a..80f787062fdffdf663edfb9c451121cfaf7614ae 100644 (file)
--- a/sim/process.cc
+++ b/sim/process.cc
@@ -39,7 +39,7 @@
 #include "config/full_system.hh"
 #include "cpu/exec_context.hh"
 #include "mem/page_table.hh"
-#include "mem/memory.hh"
+#include "mem/mem_object.hh"
 #include "mem/translating_port.hh"
 #include "sim/builder.hh"
 #include "sim/process.hh"
@@ -149,13 +149,27 @@ Process::startup()
     if (execContexts.empty())
         fatal("Process %s is not associated with any CPUs!\n", name());
 
-    initVirtMem = new TranslatingPort((system->physmem->getPort("DCACHE"))->getPeer(), pTable);
-
     // first exec context for this process... initialize & enable
     ExecContext *xc = execContexts[0];
 
     // mark this context as active so it will start ticking.
     xc->activate(0);
+
+    // Here we are grabbing the memory port of the CPU hosting the
+    // initial execution context for initialization.  In the long run
+    // this is not what we want, since it means that all
+    // initialization accesses (e.g., loading object file sections)
+    // will be done a cache block at a time through the CPU's cache.
+    // We really want something more like:
+    //
+    // memport = system->physmem->getPort();
+    // myPort.setPeer(memport);
+    // memport->setPeer(&myPort);
+    // initVirtMem = new TranslatingPort(myPort, pTable);
+    //
+    // but we need our own dummy port "myPort" that doesn't exist.
+    // In the short term it works just fine though.
+    initVirtMem = xc->getMemPort();
 }
 
 void
@@ -367,6 +381,7 @@ LiveProcess::syscall(ExecContext *xc)
     desc->doSyscall(callnum, this, xc);
 }
 
+
 LiveProcess *
 LiveProcess::create(const string &nm, System *system,
                     int stdin_fd, int stdout_fd, int stderr_fd,

diff --git a/sim/process.hh b/sim/process.hh
index ffdca819e2c6720becea5c4a360d88fe4f9f7617..68312f11576a57ab9070cb47db2eebb75182d465 100644 (file)
--- a/sim/process.hh
+++ b/sim/process.hh
@@ -40,27 +40,18 @@
 
 #include <vector>
 
-#include "arch/isa_traits.hh"
 #include "base/statistics.hh"
-#include "base/trace.hh"
-#include "mem/memory.hh"
-//#include "mem/mem_interface.hh"
-#include "mem/page_table.hh"
 #include "sim/sim_object.hh"
-#include "sim/stats.hh"
-#include "arch/isa_traits.hh"
 
 class CPUExecContext;
 class ExecContext;
 class SyscallDesc;
+class PageTable;
 class TranslatingPort;
 class System;
 
 class Process : public SimObject
 {
-  protected:
-    typedef TheISA::RegFile RegFile;
-    typedef TheISA::MachInst MachInst;
   public:
 
     /// Pointer to object representing the system this process is
@@ -198,8 +189,7 @@ class LiveProcess : public Process
 
     virtual void syscall(ExecContext *xc);
 
-    virtual SyscallDesc* getDesc(int callnum) { panic("Must be implemented."); }
-
+    virtual SyscallDesc* getDesc(int callnum) = 0;
 };
 
 

diff --git a/sim/syscall_emul.hh b/sim/syscall_emul.hh
index 667003753750e89eb86308cb2c4f598f2455a28f..9554ab3185a65504a786b1c76ab0987bbff202b5 100644 (file)
--- a/sim/syscall_emul.hh
+++ b/sim/syscall_emul.hh
@@ -48,7 +48,7 @@
 #include "base/intmath.hh"     // for RoundUp
 #include "mem/translating_port.hh"
 #include "arch/isa_traits.hh"  // for Addr
-
+#include "base/misc.hh"
 #include "base/trace.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/base.hh"

diff --git a/sim/system.cc b/sim/system.cc
index 05b41e32b56ae6822e3bbde277f7ce7b2efeb377..409e41eadfcfba7632c8572c454fc14ea843c12c 100644 (file)
--- a/sim/system.cc
+++ b/sim/system.cc
@@ -1,12 +1,12 @@
 #include "base/loader/object_file.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/exec_context.hh"
-#include "mem/memory.hh"
 #include "sim/builder.hh"
 #include "arch/isa_traits.hh"
 #include "sim/byteswap.hh"
 #include "sim/system.hh"
 #include "base/trace.hh"
+#include "mem/mem_object.hh"
 #if FULL_SYSTEM
 #include "base/remote_gdb.hh"
 #include "kern/kernel_stats.hh"
@@ -228,7 +228,7 @@ DEFINE_SIM_OBJECT_CLASS_NAME("System", System)
 
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(System)
 
-    SimObjectParam<Memory *> physmem;
+    SimObjectParam<MemObject *> physmem;
 
 END_DECLARE_SIM_OBJECT_PARAMS(System)
 

diff --git a/sim/system.hh b/sim/system.hh
index a0ba4f141c8884719a73f0f965afb3d08ad17309..0f82f81f52a8972580f4f758ce1d7ce177d5fdf7 100644 (file)
--- a/sim/system.hh
+++ b/sim/system.hh
@@ -45,7 +45,7 @@ class BaseCPU;
 class ExecContext;
 class MemoryController;
 class ObjectFile;
-class Memory;
+class MemObject;
 
 #if FULL_SYSTEM
 class Platform;
@@ -57,7 +57,7 @@ namespace Kernel { class Binning; }
 class System : public SimObject
 {
   public:
-    Memory *physmem;
+    MemObject *physmem;
     PCEventQueue pcEventQueue;
 
     std::vector<ExecContext *> execContexts;
@@ -146,7 +146,7 @@ class System : public SimObject
     struct Params
     {
         std::string name;
-        Memory *physmem;
+        MemObject *physmem;
 
 #if FULL_SYSTEM
         Tick boot_cpu_frequency;