overload READ_REG

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 5de338f2c51d9cb34fca53d2bdc8fd636d5335ff..03ac6312a7adb89eeefa72b67f7ca0742da942ea 100644 (file)
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -186,23 +186,23 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
                       "vlen %d stop %d pred %lx rdv %lx v %ld rvc2 %ld sp %lx\n",
                 xstr(INSN), INSNCODE, voffs, *src_offs, *dest_offs,
                 vlen, insn.stop_vloop(),
-                dest_pred & (1<<voffs), READ_REG(insn._rvc_rs2().reg),
-                insn._rvc_rs2().reg, insn.rvc_lwsp_imm(), READ_REG(sp.reg));
+                dest_pred & (1<<voffs), READ_REG(insn._rvc_rs2()),
+                insn._rvc_rs2().reg, insn.rvc_lwsp_imm(), READ_REG(sp));
 #endif
 #ifdef INSN_C_LWSP
     fprintf(stderr, "pre %s %x vloop %d %d %d" \
                       "vlen %d stop %d pred %lx rdv %lx rd %ld rvc2 %ld sp %lx\n",
                 xstr(INSN), INSNCODE, voffs, *src_offs, *dest_offs,
                 vlen, insn.stop_vloop(),
-                dest_pred & (1<<voffs), READ_REG(insn._rd().reg),
-                insn._rd().reg, insn.rvc_lwsp_imm(), READ_REG(sp.reg));
+                dest_pred & (1<<voffs), READ_REG(insn._rd()),
+                insn._rd().reg, insn.rvc_lwsp_imm(), READ_REG(sp));
 #endif
 #ifdef INSN_C_BEQZ
     fprintf(stderr, "pre %s %x vloop %d %ld %d" \
                       "vlen %d stop %d pred %lx rdv %lx rvc_rs1 %ld\n",
                 xstr(INSN), INSNCODE, voffs, _target_reg, *dest_offs,
                 vlen, insn.stop_vloop(),
-                dest_pred & (1<<voffs), READ_REG(insn._rvc_rs1s().reg),
+                dest_pred & (1<<voffs), READ_REG(insn._rvc_rs1s()),
                 insn._rvc_rs1s().reg);
 #endif
       #include INCLUDEFILE
@@ -221,7 +221,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
 #if defined(USING_REG_RD)
         fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx rd%lx\n",
                 xstr(INSN), INSNCODE, voffs, vlen, insn.stop_vloop(),
-                dest_pred & (1<<voffs), READ_REG(insn._rd().reg));
+                dest_pred & (1<<voffs), READ_REG(insn._rd()));
 #endif
 #if defined(USING_REG_FRD)
         fprintf(stderr, "reg %s %x vloop %d vlen %d stop %d pred %lx rd%g\n",

diff --git a/riscv/sv.cc b/riscv/sv.cc
index 1f8648b1e75184e672e2dd070a27b4e1c7a72438..7a07d809d9bc7b207b09acb19309a20637d1baa2 100644 (file)
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -161,12 +161,9 @@ reg_spec_t sv_insn_t::remap(uint64_t reg, bool intreg, int *voffs)
   }
   vloop_continue = true;
 
-  // aaand now, as it's a "vector", FINALLY we can add on the loop-offset
-  // which was passed in to the sv_insn_t constructor (by reference)
-  // and, at last, we have "parallelism" a la contiguous registers.
-  reg += *voffs; // wheww :)
-
-  spec.reg = reg;
+  // aaand now, as it's a "vector", FINALLY we can pass the loop-offset
+  spec.reg = reg + *voffs;
+  spec.offset = voffs;
   return spec;
 }
 
@@ -209,7 +206,8 @@ reg_t sv_insn_t::predicate(uint64_t reg, bool intreg, bool &zeroing)
   }
   zeroing = r->zero;
   reg = r->regidx;
-  reg_t predicate = READ_REG(reg); // macros go through processor_t state
+  reg_spec_t rs = {reg, NULL};
+  reg_t predicate = p->s.READ_REG(rs); // macros go through processor_t state
   if (r->inv)
   {
     return ~predicate;
@@ -220,6 +218,10 @@ reg_t sv_insn_t::predicate(uint64_t reg, bool intreg, bool &zeroing)
 reg_spec_t sv_insn_t::predicated(reg_spec_t const& spec, uint64_t pred)
 {
     reg_spec_t res = spec;
+    //if (spec.offset == NULL)
+    //{
+    //    return res;
+    //}
     if (pred & (1<<(*spec.offset)))
     {
         return res;
@@ -261,7 +263,9 @@ uint64_t sv_insn_t::_rvc_spoffs_imm(uint64_t elwidth, uint64_t offs)
 // for use in predicated branches. sets bit N if val=true; clears bit N if false
 uint64_t sv_insn_t::rd_bitset(reg_t reg, uint64_t bit, bool set)
 {
-    uint64_t val = READ_REG(reg);
+    //reg_spec_t rs = {reg, NULL};
+    //uint64_t val = p->s.READ_REG(rs);
+    uint64_t val = STATE.XPR[reg];
     if (set) {
         val |= (1<<bit);
     } else {
@@ -281,8 +285,9 @@ void sv_insn_t::setpc(int xlen, int vlen, reg_t &npc, reg_t addr, uint64_t offs,
         return;
     }
     if (target_reg != NULL) {
+        reg_spec_t rs = {*target_reg, NULL};
         fprintf(stderr, "setpc pre rd %ld v %lx pred %lx\n",
-                        *target_reg, READ_REG(*target_reg), prs1);
+                        *target_reg, p->s.READ_REG(rs), prs1);
     }
     if ((1<<offs) & prs1)
     {
@@ -294,7 +299,7 @@ void sv_insn_t::setpc(int xlen, int vlen, reg_t &npc, reg_t addr, uint64_t offs,
     }
     fprintf(stderr, "setpc %lx offs %ld predicate %lx rs1 %ld rs2 %ld\n",
             save_branch_rd, offs, prs1,
-            READ_REG(rs1().reg), READ_REG(rs2().reg));
+            p->s.READ_REG(rs1()), p->s.READ_REG(rs2()));
 }
 
 uint8_t sv_insn_t::reg_elwidth(reg_t reg, bool intreg)

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index da1732b0e06030eaef7207422b3aa6456756c6aa..3ad35059f9829b11daf034070db2595bb0f0260f 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -82,7 +82,11 @@ void (sv_proc_t::WRITE_RD)(sv_reg_t const& value)
 void (sv_proc_t::WRITE_REG)(reg_spec_t const& spec, sv_reg_t const& value)
 {
     //WRITE_REG( reg, value ); // XXX TODO: replace properly
-    STATE.XPR.write(spec.reg, value);
+    reg_t reg = spec.reg;
+    //if (spec.offset) {
+    //    reg += *spec.offset;
+    //}
+    STATE.XPR.write(reg, value);
 }
 
 //void (sv_proc_t::WRITE_REG)(reg_t reg, uint64_t value)
@@ -103,17 +107,19 @@ void (sv_proc_t::WRITE_RD)(uint_fast64_t value)
 }
 */
 
-/*
-sv_reg_t (sv_proc_t::READ_REG)(uint64_t i)
+reg_t (sv_proc_t::READ_REG)(reg_spec_t const& spec)
 {
-    return READ_REG ( i );
+    reg_t reg = spec.reg;
+    uint8_t elwidth = _insn->reg_elwidth(reg, true);
+    //if (spec.offset) {
+    //    reg += *spec.offset;
+    //}
+    return _insn->p->get_state()->XPR[reg]; // XXX TODO: offset
 }
-*/
 
 sv_reg_t sv_proc_t::get_intreg(reg_spec_t const&spec)
 {
-    uint8_t elwidth = _insn->reg_elwidth(spec.reg, true);
-    uint64_t data = _insn->p->get_state()->XPR[spec.reg]; // XXX TODO: offset
+    uint64_t data = READ_REG(spec);
     uint8_t bitwidth = _insn->src_bitwidth;
     return sv_reg_t(data, xlen, bitwidth);
 }

diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index af2b67fa7042d7bd0488139133eabd8bf5eb32f2..39dc5e1ca0c3f32eb903c18a93065e0087a0ca7d 100644 (file)
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -24,6 +24,7 @@
 #undef WRITE_RVC_RS2S
 #undef WRITE_RVC_FRS2S
 #undef WRITE_RD
+#undef READ_REG
 #undef RVC_SP
 #undef SHAMT
 #undef sext_xlen
@@ -76,7 +77,7 @@ public:
     void (WRITE_FRD)(freg_t value);
     void (WRITE_FRD)(float64_t value);
     void (WRITE_FRD)(float32_t value);
-    //reg_t (READ_REG)(uint64_t i);
+    reg_t (READ_REG)(reg_spec_t const& i);
 
     processor_t *p;
     sv_insn_t *_insn;