[intel-gem] Bug #16326: Fix X tile unswizzling on 965.

Apparently a bit gets flipped in the addressing for some rows of each tile.

diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 149b581d88bb151782ee626addb4f7627017a57f..c6778b16ff3718b2f2d197ebe713f09566dbf865 100644 (file)
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -106,12 +106,38 @@ static GLubyte *x_tile_swizzle(struct intel_renderbuffer *irb, struct intel_cont
        x_tile_off = xbyte & 0x1ff;
        y_tile_off = y & 7;
 
+#ifndef I915
+       /* The documentation says that X tile layout is arranged in 8 512-byte
+        * lines of pixel data.  However, that doesn't appear to be the case
+        * on GM965, tested by drawing a 128x8 quad in no_rast mode.  For lines
+        * 1,2,4, and 7 of each tile, each consecutive pair of 64-byte spans
+        * has the locations of those spans swapped.
+        */
+       switch (y_tile_off) {
+       case 1:
+       case 2:
+       case 4:
+       case 7:
+               x_tile_off ^= 64;
+               break;
+       default:
+          break;
+       }
+#endif
+
        x_tile_number = xbyte >> 9;
        y_tile_number = y >> 3;
 
        tile_off = (y_tile_off << 9) + x_tile_off;
        tile_base = (x_tile_number << 12) + y_tile_number * tile_stride;
 
+#if 0
+       printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
+              x, y, tile_off, tile_base,
+              tile_off + tile_base,
+              irb->pfPitch, tile_stride);
+#endif
+
        return buf + tile_base + tile_off;
 }