if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
return;
+ unsigned vtx_reuse_depth = 30;
+ if (radv_pipeline_has_tess(pipeline) &&
+ radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
+ vtx_reuse_depth = 14;
+ }
radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
- pipeline->graphics.vtx_reuse_depth);
+ S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
}
static void
pipeline->graphics.vtx_emit_num = 2;
}
- pipeline->graphics.vtx_reuse_depth = 30;
- if (radv_pipeline_has_tess(pipeline) &&
- radv_get_tess_eval_shader(pipeline)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
- pipeline->graphics.vtx_reuse_depth = 14;
- }
-
if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
radv_dump_pipeline_stats(device, pipeline);
}