gallium/radeon: add new HUD queries for monitoring the CP
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Mon, 30 Jan 2017 11:52:56 +0000 (12:52 +0100)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Mon, 30 Jan 2017 13:37:00 +0000 (14:37 +0100)
There are even more counters in the CP_STAT register but I think
these ones are enough for now.

v2: only read (and expose) CP_STAT on VI+

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/drivers/radeon/r600_gpu_load.c
src/gallium/drivers/radeon/r600_pipe_common.h
src/gallium/drivers/radeon/r600_query.c
src/gallium/drivers/radeon/r600_query.h

index 058006b8261107f4e3eca88fc33d09c761393de5..3b491188fb1f118269d52e3038d5de7d7284a49d 100644 (file)
 #define SRBM_STATUS2           0x0e4c
 #define SDMA_BUSY(x)           (((x) >> 5) & 0x1)
 
+#define CP_STAT                 0x8680
+#define PFP_BUSY(x)            (((x) >> 15) & 0x1)
+#define MEQ_BUSY(x)            (((x) >> 16) & 0x1)
+#define ME_BUSY(x)             (((x) >> 17) & 0x1)
+#define SURFACE_SYNC_BUSY(x)   (((x) >> 21) & 0x1)
+#define DMA_BUSY(x)            (((x) >> 22) & 0x1)
+#define SCRATCH_RAM_BUSY(x)    (((x) >> 24) & 0x1)
+#define CE_BUSY(x)             (((x) >> 26) & 0x1)
+
 #define UPDATE_COUNTER(field, mask)                                    \
        do {                                                            \
                if (mask(value))                                        \
@@ -98,6 +107,19 @@ static void r600_update_mmio_counters(struct r600_common_screen *rscreen,
 
                UPDATE_COUNTER(sdma, SDMA_BUSY);
        }
+
+       if (rscreen->chip_class >= VI) {
+               /* CP_STAT */
+               rscreen->ws->read_registers(rscreen->ws, CP_STAT, 1, &value);
+
+               UPDATE_COUNTER(pfp, PFP_BUSY);
+               UPDATE_COUNTER(meq, MEQ_BUSY);
+               UPDATE_COUNTER(me, ME_BUSY);
+               UPDATE_COUNTER(surf_sync, SURFACE_SYNC_BUSY);
+               UPDATE_COUNTER(dma, DMA_BUSY);
+               UPDATE_COUNTER(scratch_ram, SCRATCH_RAM_BUSY);
+               UPDATE_COUNTER(ce, CE_BUSY);
+       }
 }
 
 #undef UPDATE_COUNTER
@@ -223,6 +245,20 @@ static unsigned busy_index_from_type(struct r600_common_screen *rscreen,
                return BUSY_INDEX(rscreen, cb);
        case R600_QUERY_GPU_SDMA_BUSY:
                return BUSY_INDEX(rscreen, sdma);
+       case R600_QUERY_GPU_PFP_BUSY:
+               return BUSY_INDEX(rscreen, pfp);
+       case R600_QUERY_GPU_MEQ_BUSY:
+               return BUSY_INDEX(rscreen, meq);
+       case R600_QUERY_GPU_ME_BUSY:
+               return BUSY_INDEX(rscreen, me);
+       case R600_QUERY_GPU_SURF_SYNC_BUSY:
+               return BUSY_INDEX(rscreen, surf_sync);
+       case R600_QUERY_GPU_DMA_BUSY:
+               return BUSY_INDEX(rscreen, dma);
+       case R600_QUERY_GPU_SCRATCH_RAM_BUSY:
+               return BUSY_INDEX(rscreen, scratch_ram);
+       case R600_QUERY_GPU_CE_BUSY:
+               return BUSY_INDEX(rscreen, ce);
        default:
                unreachable("invalid query type");
        }
index 9118b6bcf846306ec286e07a78088e204a876e03..fb5bf75df153f650fc4302f6091b2c4c31e53f66 100644 (file)
@@ -377,6 +377,15 @@ union r600_mmio_counters {
 
                /* SRBM_STATUS2 */
                struct r600_mmio_counter sdma;
+
+               /* CP_STAT */
+               struct r600_mmio_counter pfp;
+               struct r600_mmio_counter meq;
+               struct r600_mmio_counter me;
+               struct r600_mmio_counter surf_sync;
+               struct r600_mmio_counter dma;
+               struct r600_mmio_counter scratch_ram;
+               struct r600_mmio_counter ce;
        } named;
        unsigned array[0];
 };
index 1747026d0dc1492209e10a47dd201e301582fa86..05741d33c9fa67b3d1a97c5913c20b2b2ad8f7b8 100644 (file)
@@ -163,6 +163,13 @@ static bool r600_query_sw_begin(struct r600_common_context *rctx,
        case R600_QUERY_GPU_CP_BUSY:
        case R600_QUERY_GPU_CB_BUSY:
        case R600_QUERY_GPU_SDMA_BUSY:
+       case R600_QUERY_GPU_PFP_BUSY:
+       case R600_QUERY_GPU_MEQ_BUSY:
+       case R600_QUERY_GPU_ME_BUSY:
+       case R600_QUERY_GPU_SURF_SYNC_BUSY:
+       case R600_QUERY_GPU_DMA_BUSY:
+       case R600_QUERY_GPU_SCRATCH_RAM_BUSY:
+       case R600_QUERY_GPU_CE_BUSY:
                query->begin_result = r600_begin_counter(rctx->screen,
                                                         query->b.type);
                break;
@@ -271,6 +278,13 @@ static bool r600_query_sw_end(struct r600_common_context *rctx,
        case R600_QUERY_GPU_CP_BUSY:
        case R600_QUERY_GPU_CB_BUSY:
        case R600_QUERY_GPU_SDMA_BUSY:
+       case R600_QUERY_GPU_PFP_BUSY:
+       case R600_QUERY_GPU_MEQ_BUSY:
+       case R600_QUERY_GPU_ME_BUSY:
+       case R600_QUERY_GPU_SURF_SYNC_BUSY:
+       case R600_QUERY_GPU_DMA_BUSY:
+       case R600_QUERY_GPU_SCRATCH_RAM_BUSY:
+       case R600_QUERY_GPU_CE_BUSY:
                query->end_result = r600_end_counter(rctx->screen,
                                                     query->b.type,
                                                     query->begin_result);
@@ -1771,6 +1785,13 @@ static struct pipe_driver_query_info r600_driver_query_list[] = {
        X("GPU-cp-busy",                GPU_CP_BUSY,            UINT64, AVERAGE),
        X("GPU-cb-busy",                GPU_CB_BUSY,            UINT64, AVERAGE),
        X("GPU-sdma-busy",              GPU_SDMA_BUSY,          UINT64, AVERAGE),
+       X("GPU-pfp-busy",               GPU_PFP_BUSY,           UINT64, AVERAGE),
+       X("GPU-meq-busy",               GPU_MEQ_BUSY,           UINT64, AVERAGE),
+       X("GPU-me-busy",                GPU_ME_BUSY,            UINT64, AVERAGE),
+       X("GPU-surf-sync-busy",         GPU_SURF_SYNC_BUSY,     UINT64, AVERAGE),
+       X("GPU-dma-busy",               GPU_DMA_BUSY,           UINT64, AVERAGE),
+       X("GPU-scratch-ram-busy",       GPU_SCRATCH_RAM_BUSY,   UINT64, AVERAGE),
+       X("GPU-ce-busy",                GPU_CE_BUSY,            UINT64, AVERAGE),
 
        X("temperature",                GPU_TEMPERATURE,        UINT64, AVERAGE),
        X("shader-clock",               CURRENT_GPU_SCLK,       HZ, AVERAGE),
@@ -1785,10 +1806,14 @@ static unsigned r600_get_num_queries(struct r600_common_screen *rscreen)
 {
        if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
                return ARRAY_SIZE(r600_driver_query_list);
-       else if (rscreen->info.drm_major == 3)
-               return ARRAY_SIZE(r600_driver_query_list) - 3;
+       else if (rscreen->info.drm_major == 3) {
+               if (rscreen->chip_class >= VI)
+                       return ARRAY_SIZE(r600_driver_query_list) - 3;
+               else
+                       return ARRAY_SIZE(r600_driver_query_list) - 10;
+       }
        else
-               return ARRAY_SIZE(r600_driver_query_list) - 18;
+               return ARRAY_SIZE(r600_driver_query_list) - 25;
 }
 
 static int r600_get_driver_query_info(struct pipe_screen *screen,
index 0b32793c6573640f36bea05d0e16514c64fb57b0..5de80d966c76c1e721609791fba1a0a93293256d 100644 (file)
@@ -86,6 +86,13 @@ enum {
        R600_QUERY_GPU_CP_BUSY,
        R600_QUERY_GPU_CB_BUSY,
        R600_QUERY_GPU_SDMA_BUSY,
+       R600_QUERY_GPU_PFP_BUSY,
+       R600_QUERY_GPU_MEQ_BUSY,
+       R600_QUERY_GPU_ME_BUSY,
+       R600_QUERY_GPU_SURF_SYNC_BUSY,
+       R600_QUERY_GPU_DMA_BUSY,
+       R600_QUERY_GPU_SCRATCH_RAM_BUSY,
+       R600_QUERY_GPU_CE_BUSY,
        R600_QUERY_NUM_COMPILATIONS,
        R600_QUERY_NUM_SHADERS_CREATED,
        R600_QUERY_BACK_BUFFER_PS_DRAW_RATIO,