cpu: vexriscv: allow cpu_reset_address to be overridden

Allow the cpu_reset_address value to be overridden, for example allowing
it to be a signal.  That way the reset address can be modified after
synthesis, in dual-core or debug situations.

Signed-off-by: Sean Cross <sean@xobs.io>

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 1edcc3f7bba90c376b50aef7d8a4fb225a7ecf6e..db05e1fd4aadb61493a04cd3cadb9f3369fac6b0 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -21,6 +21,7 @@ class VexRiscv(Module, AutoCSR):
         self.reset = Signal()
         self.ibus = ibus = wishbone.Interface()
         self.dbus = dbus = wishbone.Interface()
+        self.cpu_reset_address = cpu_reset_address
 
         self.interrupt = Signal(32)
 
@@ -28,7 +29,7 @@ class VexRiscv(Module, AutoCSR):
                 i_clk=ClockSignal(),
                 i_reset=ResetSignal() | self.reset,
 
-                i_externalResetVector=cpu_reset_address,
+                i_externalResetVector=self.cpu_reset_address,
                 i_externalInterruptArray=self.interrupt,
                 i_timerInterrupt=0,