Update README
authorClifford Wolf <clifford@clifford.at>
Sat, 4 May 2019 06:01:39 +0000 (08:01 +0200)
committerClifford Wolf <clifford@clifford.at>
Sat, 4 May 2019 06:01:39 +0000 (08:01 +0200)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
README.md

index d21d60c979d15d450f2789650022e361f54abb6a..195329a372b7fbede2bab1eec0e1cdf021e9177f 100644 (file)
--- a/README.md
+++ b/README.md
@@ -259,11 +259,7 @@ for them:
 
 - The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
 
-- The ``config`` keyword and library map files
-
-- The ``disable``, ``primitive`` and ``specify`` statements
-
-- Latched logic (is synthesized as logic with feedback loops)
+- The ``config`` and ``disable`` keywords and library map files
 
 
 Verilog Attributes and non-standard features