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Update README
author
Clifford Wolf
<clifford@clifford.at>
Sat, 4 May 2019 06:01:39 +0000
(08:01 +0200)
committer
Clifford Wolf
<clifford@clifford.at>
Sat, 4 May 2019 06:01:39 +0000
(08:01 +0200)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
README.md
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b/README.md
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README.md
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README.md
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for them:
- The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
-- The ``config`` keyword and library map files
-
-- The ``disable``, ``primitive`` and ``specify`` statements
-
-- Latched logic (is synthesized as logic with feedback loops)
+- The ``config`` and ``disable`` keywords and library map files
Verilog Attributes and non-standard features