Merge remote-tracking branch 'origin/master' into xc7srl

diff --cc techlibs/xilinx/synth_xilinx.cc
index e84a6714baea2b22161d3f102177d3824a60ab36,d66722195e0af30a3bd69ebe4d01663c29c68dbc..1449e792f034f8f2cbcc7536f617bee16b560cc9
--- 1/techlibs/xilinx/synth_xilinx.cc
--- 2/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -124,14 -118,13 +124,15 @@@ struct SynthXilinxPass : public Pas
                log("        clean\n");
                log("\n");
                log("    map_luts:\n");
 -              log("        techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n");
 +              log("        opt -full\n");
 +              log("        techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v\n");
                log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
                log("        clean\n");
 -              log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 +              log("        shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n");
 +              log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
                log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
                log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
+               log("        clean\n");
                log("\n");
                log("    check:\n");
                log("        hierarchy -check\n");
@@@ -300,15 -275,13 +301,16 @@@
  
                if (check_label(active, run_from, run_to, "map_luts"))
                {
 -                      Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
 +                      Pass::call(design, "opt -full");
 +                      Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
                        Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
                        Pass::call(design, "clean");
 -                      Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 +                      if (!nosrl)
 +                              Pass::call(design, "shregmap -minlen 3 -init -params -enpol any_or_none");
 +                      Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
                        Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
                                        "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+                       Pass::call(design, "clean");
                }
  
                if (check_label(active, run_from, run_to, "check"))