Add SB_CARRY to ice40_opt test

diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys
index 18e0d2b8a9fa48a4205f20b15e9af7dca6f4d0d8..b17c69c919ec0725265749d25934a73184302378 100644 (file)
--- a/tests/ice40/ice40_opt.ys
+++ b/tests/ice40/ice40_opt.ys
@@ -1,5 +1,5 @@
 read_verilog -icells -formal <<EOT
-module top(input CI, I0, output CO, O);
+module top(input CI, I0, output [1:0] CO, output O);
     wire A = 1'b0, B = 1'b0;
        \$__ICE40_CARRY_WRAPPER #(
                //    A[0]: 1010 1010 1010 1010
@@ -7,18 +7,20 @@ module top(input CI, I0, output CO, O);
                //    A[2]: 1111 0000 1111 0000
                //    A[3]: 1111 1111 0000 0000
                .LUT(~16'b 0110_1001_1001_0110)
-       ) fadd (
+       ) u0 (
                .A(A),
                .B(B),
                .CI(CI),
                .I0(I0),
                .I3(CI),
-               .CO(CO),
+               .CO(CO[0]),
                .O(O)
        );
+    SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1]));
 endmodule
 EOT
 
 equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
 design -load postopt
+select -assert-count 1 t:*
 select -assert-count 1 t:$lut