i965: Rename various gen6 #defines to match the documentation.

This should make it easier to cross-reference the code and hardware
documentation, as well as clear up any confusion on whether constants
like CMD_3D_WM_STATE mean WM_STATE (pre-gen6) or 3DSTATE_WM (gen6+).

This does not rename any pre-gen6 defines.

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index af7d6df9353db8560f064190823d5f970ad30b1b..ea6ac34048250d0a44e19b0b9bb570d919be7010 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -845,7 +845,7 @@
 # define GEN6_BINDING_TABLE_MODIFY_GS  (1 << 9)
 # define GEN6_BINDING_TABLE_MODIFY_PS  (1 << 12)
 
-#define CMD_3D_SAMPLER_STATE_POINTERS                  0x7802 /* SNB+ */
+#define _3DSTATE_SAMPLER_STATE_POINTERS                0x7802 /* GEN6+ */
 # define PS_SAMPLER_STATE_CHANGE                               (1 << 12)
 # define GS_SAMPLER_STATE_CHANGE                               (1 << 9)
 # define VS_SAMPLER_STATE_CHANGE                               (1 << 8)
@@ -886,22 +886,22 @@
 #define CMD_INDEX_BUFFER              0x780a
 #define CMD_VF_STATISTICS_965          0x780b
 #define CMD_VF_STATISTICS_GM45        0x680b
-#define CMD_3D_CC_STATE_POINTERS      0x780e /* GEN6+ */
+#define _3DSTATE_CC_STATE_POINTERS             0x780e /* GEN6+ */
 
-#define CMD_URB                                        0x7805 /* GEN6+ */
+#define _3DSTATE_URB                           0x7805 /* GEN6+ */
 # define GEN6_URB_VS_SIZE_SHIFT                                16
 # define GEN6_URB_VS_ENTRIES_SHIFT                     0
 # define GEN6_URB_GS_ENTRIES_SHIFT                     8
 # define GEN6_URB_GS_SIZE_SHIFT                                0
 
-#define CMD_VIEWPORT_STATE_POINTERS                    0x780d /* GEN6+ */
+#define _3DSTATE_VIEWPORT_STATE_POINTERS       0x780d /* GEN6+ */
 # define GEN6_CC_VIEWPORT_MODIFY                       (1 << 12)
 # define GEN6_SF_VIEWPORT_MODIFY                       (1 << 11)
 # define GEN6_CLIP_VIEWPORT_MODIFY                     (1 << 10)
 
-#define CMD_3D_SCISSOR_STATE_POINTERS          0x780f /* GEN6+ */
+#define _3DSTATE_SCISSOR_STATE_POINTERS                0x780f /* GEN6+ */
 
-#define CMD_3D_VS_STATE                      0x7810 /* GEN6+ */
+#define _3DSTATE_VS                            0x7810 /* GEN6+ */
 /* DW2 */
 # define GEN6_VS_SPF_MODE                              (1 << 31)
 # define GEN6_VS_VECTOR_MASK_ENABLE                    (1 << 30)
@@ -919,7 +919,7 @@
 # define GEN6_VS_CACHE_DISABLE                         (1 << 1)
 # define GEN6_VS_ENABLE                                        (1 << 0)
 
-#define CMD_3D_GS_STATE                      0x7811 /* GEN6+ */
+#define _3DSTATE_GS                            0x7811 /* GEN6+ */
 /* DW2 */
 # define GEN6_GS_SPF_MODE                              (1 << 31)
 # define GEN6_GS_VECTOR_MASK_ENABLE                    (1 << 30)
@@ -937,7 +937,7 @@
 /* DW6 */
 # define GEN6_GS_ENABLE                                        (1 << 15)
 
-#define CMD_3D_CLIP_STATE                    0x7812 /* GEN6+ */
+#define _3DSTATE_CLIP                          0x7812 /* GEN6+ */
 /* DW1 */
 # define GEN6_CLIP_STATISTICS_ENABLE                   (1 << 10)
 /**
@@ -967,7 +967,7 @@
 # define GEN6_CLIP_MAX_POINT_WIDTH_SHIFT               6
 # define GEN6_CLIP_FORCE_ZERO_RTAINDEX                 (1 << 5)
 
-#define CMD_3D_SF_STATE                                0x7813 /* GEN6+ */
+#define _3DSTATE_SF                            0x7813 /* GEN6+ */
 /* DW1 */
 # define GEN6_SF_NUM_OUTPUTS_SHIFT                     22
 # define GEN6_SF_SWIZZLE_ENABLE                                (1 << 21)
@@ -1044,7 +1044,7 @@
 /* DW18: attr 0-7 wrap shortest enables */
 /* DW19: attr 8-16 wrap shortest enables */
 
-#define CMD_3D_WM_STATE                      0x7814 /* GEN6+ */
+#define _3DSTATE_WM                            0x7814 /* GEN6+ */
 /* DW1: kernel pointer */
 /* DW2 */
 # define GEN6_WM_SPF_MODE                              (1 << 31)
@@ -1107,15 +1107,15 @@
 /* DW7: kernel 1 pointer */
 /* DW8: kernel 2 pointer */
 
-#define CMD_3D_CONSTANT_VS_STATE             0x7815 /* GEN6+ */
-#define CMD_3D_CONSTANT_GS_STATE             0x7816 /* GEN6+ */
-#define CMD_3D_CONSTANT_PS_STATE             0x7817 /* GEN6+ */
+#define _3DSTATE_CONSTANT_VS                 0x7815 /* GEN6+ */
+#define _3DSTATE_CONSTANT_GS                 0x7816 /* GEN6+ */
+#define _3DSTATE_CONSTANT_PS                 0x7817 /* GEN6+ */
 # define GEN6_CONSTANT_BUFFER_3_ENABLE                 (1 << 15)
 # define GEN6_CONSTANT_BUFFER_2_ENABLE                 (1 << 14)
 # define GEN6_CONSTANT_BUFFER_1_ENABLE                 (1 << 13)
 # define GEN6_CONSTANT_BUFFER_0_ENABLE                 (1 << 12)
 
-#define CMD_3D_SAMPLE_MASK                     0x7818 /* GEN6+ */
+#define _3DSTATE_SAMPLE_MASK                   0x7818 /* GEN6+ */
 
 #define CMD_DRAW_RECT                 0x7900
 #define CMD_BLEND_CONSTANT_COLOR      0x7901
@@ -1134,7 +1134,7 @@
 /* DW2: SVB index */
 /* DW3: SVB maximum index */
 
-#define CMD_3D_MULTISAMPLE                     0x790d /* SNB+ */
+#define _3DSTATE_MULTISAMPLE                   0x790d /* GEN6+ */
 /* DW1 */
 # define MS_PIXEL_LOCATION_CENTER                      (0 << 4)
 # define MS_PIXEL_LOCATION_UPPER_LEFT                  (1 << 4)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index a91b0528fac61394f51b5727ce26fd39a55f2fab..c49ebe64a6035eb50c29f7214d221ef19148ea14 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -492,14 +492,14 @@ static void upload_invarient_state( struct brw_context *brw )
       int i;
 
       BEGIN_BATCH(3);
-      OUT_BATCH(CMD_3D_MULTISAMPLE << 16 | (3 - 2));
+      OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (3 - 2));
       OUT_BATCH(MS_PIXEL_LOCATION_CENTER |
                MS_NUMSAMPLES_1);
       OUT_BATCH(0); /* positions for 4/8-sample */
       ADVANCE_BATCH();
 
       BEGIN_BATCH(2);
-      OUT_BATCH(CMD_3D_SAMPLE_MASK << 16 | (2 - 2));
+      OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2));
       OUT_BATCH(1);
       ADVANCE_BATCH();
 

diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index c2631a7b4df6d947759bd806cc418e3e94ae40df..dbcdc5b86936ddc7687dfc9d4c702b48e81572a9 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -278,7 +278,7 @@ static void upload_cc_state_pointers(struct brw_context *brw)
    struct intel_context *intel = &brw->intel;
 
    BEGIN_BATCH(4);
-   OUT_BATCH(CMD_3D_CC_STATE_POINTERS << 16 | (4 - 2));
+   OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
    OUT_RELOC(brw->cc.blend_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
    OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
    OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);

diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c
index e25d1bf78796bf78e62c7804e73973785c13bec9..38c98f30efbeac309f4d5105c8d176a840201d87 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -58,7 +58,7 @@ upload_clip_state(struct brw_context *brw)
    userclip = (1 << brw_count_bits(ctx->Transform.ClipPlanesEnabled)) - 1;
 
    BEGIN_BATCH(4);
-   OUT_BATCH(CMD_3D_CLIP_STATE << 16 | (4 - 2));
+   OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2));
    OUT_BATCH(GEN6_CLIP_STATISTICS_ENABLE);
    OUT_BATCH(GEN6_CLIP_ENABLE |
             GEN6_CLIP_API_OGL |

diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index 6127b9197a1b880acaaecc6d83ed4e509b849e51..7296c7cd1b04268c988840f0235c4e1fa2b2c6ae 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -37,7 +37,7 @@ upload_gs_state(struct brw_context *brw)
 
    /* Disable all the constant buffers. */
    BEGIN_BATCH(5);
-   OUT_BATCH(CMD_3D_CONSTANT_GS_STATE << 16 | (5 - 2));
+   OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (5 - 2));
    OUT_BATCH(0);
    OUT_BATCH(0);
    OUT_BATCH(0);
@@ -46,7 +46,7 @@ upload_gs_state(struct brw_context *brw)
 
    if (brw->gs.prog_bo) {
       BEGIN_BATCH(7);
-      OUT_BATCH(CMD_3D_GS_STATE << 16 | (7 - 2));
+      OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
       OUT_RELOC(brw->gs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
       OUT_BATCH(GEN6_GS_SPF_MODE |
                (0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
@@ -62,7 +62,7 @@ upload_gs_state(struct brw_context *brw)
       ADVANCE_BATCH();
    } else {
       BEGIN_BATCH(7);
-      OUT_BATCH(CMD_3D_GS_STATE << 16 | (7 - 2));
+      OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
       OUT_BATCH(0); /* prog_bo */
       OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
                (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));

diff --git a/src/mesa/drivers/dri/i965/gen6_sampler_state.c b/src/mesa/drivers/dri/i965/gen6_sampler_state.c
index fc5d391c3cfe132593fad2307d3249c14d66c8fe..f65c651bdff9b1d43fb7329e77f1860840d4fd28 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sampler_state.c
@@ -36,7 +36,7 @@ upload_sampler_state_pointers(struct brw_context *brw)
    struct intel_context *intel = &brw->intel;
 
    BEGIN_BATCH(4);
-   OUT_BATCH(CMD_3D_SAMPLER_STATE_POINTERS << 16 |
+   OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS << 16 |
             VS_SAMPLER_STATE_CHANGE |
             GS_SAMPLER_STATE_CHANGE |
             PS_SAMPLER_STATE_CHANGE |

diff --git a/src/mesa/drivers/dri/i965/gen6_scissor_state.c b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
index b57126c7938e054acf5d72459c7cdb332fb9470a..12b65826ae99a98531f1258e99c6c43194546953 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_scissor_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_scissor_state.c
@@ -92,7 +92,7 @@ static void upload_scissor_state_pointers(struct brw_context *brw)
    struct intel_context *intel = &brw->intel;
 
    BEGIN_BATCH(2);
-   OUT_BATCH(CMD_3D_SCISSOR_STATE_POINTERS << 16 | (2 - 2));
+   OUT_BATCH(_3DSTATE_SCISSOR_STATE_POINTERS << 16 | (2 - 2));
    OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
    ADVANCE_BATCH();
 

diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 45c148baedd275153ba9aa538f00a6bb7b480547..f27782935d42ac3930dfe5401d205891a90263b3 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -237,7 +237,7 @@ upload_sf_state(struct brw_context *brw)
    }
 
    BEGIN_BATCH(20);
-   OUT_BATCH(CMD_3D_SF_STATE << 16 | (20 - 2));
+   OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2));
    OUT_BATCH(dw1);
    OUT_BATCH(dw2);
    OUT_BATCH(dw3);

diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c
index de97fd3783d34907d0fb06b819b1b84ad7899e35..fc46c4cb79e3373eec99991dea33675d0c9b4bd6 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -60,7 +60,7 @@ upload_urb(struct brw_context *brw)
    assert(!brw->gs.prog_bo || brw->urb.vs_size < 5);
 
    BEGIN_BATCH(3);
-   OUT_BATCH(CMD_URB << 16 | (3 - 2));
+   OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2));
    OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) |
             ((brw->urb.nr_vs_entries) << GEN6_URB_VS_ENTRIES_SHIFT));
    OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) |

diff --git a/src/mesa/drivers/dri/i965/gen6_viewport_state.c b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
index d691bbebc83f9cde921090ee04e3235cd00520e2..cd7d209e3eadb74c795dbbc77750a16985cdbf7b 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_viewport_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
@@ -117,7 +117,7 @@ static void upload_viewport_state_pointers(struct brw_context *brw)
    struct intel_context *intel = &brw->intel;
 
    BEGIN_BATCH(4);
-   OUT_BATCH(CMD_VIEWPORT_STATE_POINTERS << 16 | (4 - 2) |
+   OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS << 16 | (4 - 2) |
             GEN6_CC_VIEWPORT_MODIFY |
             GEN6_SF_VIEWPORT_MODIFY |
             GEN6_CLIP_VIEWPORT_MODIFY);

diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index ed132bdbd9329d553202a29897801a629b999a02..e68c0ac261c963e1b30f9edd4df92645b068bb13 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -47,7 +47,7 @@ upload_vs_state(struct brw_context *brw)
    if (brw->vs.prog_data->nr_params == 0 && !ctx->Transform.ClipPlanesEnabled) {
       /* Disable the push constant buffers. */
       BEGIN_BATCH(5);
-      OUT_BATCH(CMD_3D_CONSTANT_VS_STATE << 16 | (5 - 2));
+      OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
@@ -112,7 +112,7 @@ upload_vs_state(struct brw_context *brw)
       assert(param_regs <= 32);
 
       BEGIN_BATCH(5);
-      OUT_BATCH(CMD_3D_CONSTANT_VS_STATE << 16 |
+      OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 |
                GEN6_CONSTANT_BUFFER_0_ENABLE |
                (5 - 2));
       OUT_RELOC(constant_bo,
@@ -127,7 +127,7 @@ upload_vs_state(struct brw_context *brw)
    }
 
    BEGIN_BATCH(6);
-   OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
+   OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
    OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
    OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
             GEN6_VS_FLOATING_POINT_MODE_ALT |

diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 2ae0c093ebe6a07a49d7b233a48e19292b7c683d..78901ecac576232a7752f71ddffa7b13808a8d32 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -107,7 +107,7 @@ upload_wm_state(struct brw_context *brw)
    if (brw->wm.prog_data->nr_params == 0) {
       /* Disable the push constant buffers. */
       BEGIN_BATCH(5);
-      OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | (5 - 2));
+      OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
@@ -115,7 +115,7 @@ upload_wm_state(struct brw_context *brw)
       ADVANCE_BATCH();
    } else {
       BEGIN_BATCH(5);
-      OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 |
+      OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
                GEN6_CONSTANT_BUFFER_0_ENABLE |
                (5 - 2));
       OUT_RELOC(brw->wm.push_const_bo,
@@ -181,7 +181,7 @@ upload_wm_state(struct brw_context *brw)
       GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
 
    BEGIN_BATCH(9);
-   OUT_BATCH(CMD_3D_WM_STATE << 16 | (9 - 2));
+   OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
    OUT_RELOC(brw->wm.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
    OUT_BATCH(dw2);
    OUT_BATCH(0); /* scratch space base offset */