Try a different approach with 'muxcover'

diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index c814f3a9669dc0c9669d3ccabc746847ee0dbe44..258b6c3dec039ed343fbd9e606e9210fa599cdce 100644 (file)
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -143,75 +143,23 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
 endmodule
 
 `ifndef NO_MUXFN
-module \$shiftx (A, B, Y);
-  parameter A_SIGNED = 0;
-  parameter B_SIGNED = 0;
-  parameter A_WIDTH = 1;
-  parameter B_WIDTH = 1;
-  parameter Y_WIDTH = 1;
+module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
+    input A, B, C, D, E, F, G, H, S, T, U;
+    output Y;
 
-  input [A_WIDTH-1:0] A;
-  input [B_WIDTH-1:0] B;
-  output [Y_WIDTH-1:0] Y;
+       wire [1:0] Z;
+    assign Z = T ? (S ? {D,H} : {C,G}) :
+                   (S ? {B,F} : {A,E});
+    MUXF7 fpga_muxf7 (.I0(Z[0]), .I1(Z[1]), .S(U), .O(Y));
+endmodule
 
-  parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
-  parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
+module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
+    input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
+    output Y;
 
-  generate
-    genvar i, j;
-    if (B_SIGNED) begin
-      if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
-        // Optimisation to remove B_SIGNED if sign bit of B is constant-0
-        \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
-      else
-        wire _TECHMAP_FAIL_ = 1;
-    end
-    else if (Y_WIDTH > 1) begin
-      wire _TECHMAP_FAIL_ = 1;
-    end
-    else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
-      wire _TECHMAP_FAIL_ = 1;
-    end
-    else if (B_WIDTH == 3) begin
-      localparam a_width0 = 2 ** 2;
-      localparam a_widthN = A_WIDTH - a_width0;
-      wire T0, T1;
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[a_width0-1:0]),       .B(B[2-1:0]),                .Y(T0));
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
-      MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
-    end
-    else if (B_WIDTH == 4) begin
-      localparam a_width0 = 2 ** 2;
-      localparam num_mux8 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH - num_mux8*a_width0;
-      wire [4-1:0] T;
-      wire T0, T1;
-      for (i = 0; i < 4; i++)
-        if (i < num_mux8)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]),                .Y(T[i]));
-        else if (i == num_mux8 && a_widthN > 0)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
-        else
-          assign T[i] = 1'bx;
-      MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
-      MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
-      MUXF8 fpga_mux_2 (.I0(T0),   .I1(T1),   .S(B[3]), .O(Y));
-    end
-    else begin
-      localparam a_width0 = 2 ** 4;
-      localparam num_mux16 = A_WIDTH / a_width0;
-      localparam a_widthN = A_WIDTH - num_mux16*a_width0;
-      wire [(2**(B_WIDTH-4))-1:0] T;
-      for (i = 0; i < 2 ** (B_WIDTH-4); i++)
-        if (i < num_mux16)
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4),                .Y_WIDTH(Y_WIDTH)) fpga_shiftx      (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]),                .Y(T[i]));
-        else if (i == num_mux16 && a_widthN > 0) begin
-          \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
-        end
-        else
-          assign T[i] = 1'bx;
-      \$shiftx  #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
-    end
-  endgenerate
+       wire [1:0] Z;
+       \$_MUX8_ fpga_mux8_0 (.A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G), .H(H), .S(S), .T(T), .U(U), .Y(Z[0]));
+       \$_MUX8_ fpga_mux8_1 (.A(I), .B(J), .C(K), .D(L), .E(M), .F(N), .G(O), .H(P), .S(S), .T(T), .U(U), .Y(Z[1]));
+    MUXF8 fpga_muxf8 (.I0(Z[0]), .I1(Z[1]), .S(V), .O(Y));
 endmodule
 `endif // NO_MUXFN

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 524c54d3bc50a0b9887abd0a34209341b8fd4d3b..5652806f7c0b9bf0734469c74422b2a3b0b9ba82 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -292,36 +292,37 @@ struct SynthXilinxPass : public Pass
                        Pass::call(design, "dffsr2dff");
                        Pass::call(design, "dff2dffe");
 
+                       // shregmap -tech xilinx can cope with $shiftx and $mux
+                       //   cells for identifying variable-length shift registers,
+                       //   so attempt to convert $pmux-es to the former
+                       // Also: wide multiplexer inference benefits from this too
+                       if (!nosrl || !nomux)
+                               Pass::call(design, "pmux2shiftx");
+
+                       Pass::call(design, "opt -full");
                        if (!nocarry) {
                                if (vpr)
-                                       Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
+                                       Pass::call(design, "techmap -map +/techmap.v  -D _EXPLICIT_CARRY -map +/xilinx/arith_map.v");
                                else
-                                       Pass::call(design, "techmap -map +/xilinx/arith_map.v");
+                                       Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
+                       }
+                       else  {
+                               Pass::call(design, "techmap");
                        }
+                       Pass::call(design, "opt -fast");
+
+                       // shregmap with '-tech xilinx' infers variable length shift regs
+                       if (!nosrl)
+                               Pass::call(design, "shregmap -tech xilinx -minlen 3");
+
+                       if (!nomux)
+                               Pass::call(design, "muxcover -mux8 -mux16");
 
                        Pass::call(design, "opt -fast");
                }
 
                if (check_label(active, run_from, run_to, "map_cells"))
                {
-                       // shregmap -tech xilinx can cope with $shiftx and $mux
-                       //   cells for identifying variable-length shift registers,
-                       //   so attempt to convert $pmux-es to the former
-                       // Also: wide multiplexer inference benefits from this too
-                       if (!nosrl || !nomux)
-                               Pass::call(design, "pmux2shiftx");
-
-                       if (!nosrl) {
-                               // shregmap operates on bit-level flops, not word-level,
-                               //   so break those down here
-                               Pass::call(design, "simplemap t:$dff t:$dffe");
-                               // pmux2shiftx can leave behind a $pmux with a single entry
-                               //   -- need this to clean that up before shregmap
-                               Pass::call(design, "opt_expr -mux_undef");
-                               // shregmap with '-tech xilinx' infers variable length shift regs
-                               Pass::call(design, "shregmap -tech xilinx -minlen 3");
-                       }
-
                        std::string define;
                        if (nomux)
                                define += " -D NO_MUXFN";
@@ -331,7 +332,6 @@ struct SynthXilinxPass : public Pass
 
                if (check_label(active, run_from, run_to, "map_luts"))
                {
-                       Pass::call(design, "opt -full");
                        Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
                        if (abc == "abc9")
                                Pass::call(design, abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : ""));